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Development Programming Languages FPGA

Effective Verilog Learning with Intel FPGAs

The step-by-step learners guide through Intel and other FPGAs based system development.
Rating: 4.1 out of 54.1 (41 ratings)
237 students
Created by Muhammad Tahir Rana
Last updated 11/2020
English
English [Auto]
30-Day Money-Back Guarantee

What you'll learn

  • Hardware Description Language ( in this case, Verilog), different design constructs, efficient development handling, TCL for Verification-Automation etc
  • Our Target will be Intel FPGAs and Development tools. Although three reference FPGA boards will be presented, and will be discussed, but I will try to make student as Independent as possible from FPGA brands and boards, so that they can adopt other FPGAs and development boards pretty easily.
  • The goal of this course is to train young professionals for independent development. We will walk through the effective Language constructs and tools, avoiding unnecessary theoretical details.
  • All Examples and software will be done in Windows (10) environment. Students with Windows 7 and 8 may also join the course. (Sorry Linux Guys)
  • Development board is optional. All Software used in this course is freely available. But a computer with Windows Operating system is a must.
  • We will analyze already developed codes, so that I may have time to explain codes and syntax in more detail. This step I took to shrink course duration.
  • 2 Intel FPGA based development Boards are introduced. 1 Xilinx FPGA based development Board and Xilinx tool chain is also introduced as additional part of the course.

Course content

9 sections • 86 lectures • 14h 2m total length

  • Preview06:09
  • What is FPGA
    18:02
  • How to Choose a FPGA
    19:22
  • Part numbers, Pin Numbers of FPGAs
    07:28
  • Selecting a Development board
    08:43
  • Details on MAX1000 baord
    04:49
  • Details on De0-Nano board
    05:40
  • I/O pins
    05:30
  • Clock pins
    06:15
  • JTAG Interface pins
    04:03
  • Power pins, pin Banks, Drive-Powers
    10:28
  • Quiz
    2 questions

  • Preview06:49
  • Installing USB blaster software for DE0-Nano
    02:42
  • Installing USB blaster software for MAX1000
    04:22
  • Quiz
    1 question

  • Introduction to Hardware Description Languages (HDLs)
    11:28
  • Verilog Fundamentals 1
    17:31
  • Verilog Fundamentals 2
    08:56
  • Verilog Fundamentals 3
    06:06
  • Verilog Fundamentals 4
    02:53
  • Verilog Fundamentals 5
    02:28
  • Verilog Fundamentals 6 : Operators
    15:33
  • D Flip-flop theory
    04:10
  • Our beloved D Flip-flop : ModelSim
    05:54
  • Testbench theory
    06:09
  • Verification of D Flip-flop In ModelSim: The RTL Simulation
    07:28
  • Introduction to Quartus II Lite software
    15:06
  • Programming Max1000 board with D-Flip Flop
    11:58
  • Programming DE0-Nano with D-Flip Flop
    15:27
  • Gates
    07:46
  • Multi-gate designs
    05:57
  • Full Adder and multi-bit adder : The Instances in Verilog
    12:18
  • Post Fitting or Gate level simulation using Testbench using Quartus-ModelSim
    13:00
  • Quiz
    1 question

  • Preview10:42
  • Simple MAC (Multiplication And Accumulation) block
    04:45
  • MAC testing
    10:27
  • Counter Design
    10:17
  • Counter Verification
    06:19
  • Programming Counter in DE0 Nano
    10:50
  • Programming Counter in MAX1000
    07:33
  • Introduction to ATOM Editor
    10:04
  • Two always blocks : Code Style explained
    11:32
  • Encoders
    07:06
  • Parameterized Designs: RAM design
    08:37
  • RAM testing
    13:21
  • Case Constructs
    05:25
  • Case Example and verification
    08:04
  • Synthesizable, and non-Synthesizable Verilog
    06:45
  • Quiz
    1 question

  • Preview08:11
  • Verification automation using TCL: Method 1
    08:53
  • Verification automation using TCL: Method 2
    06:36
  • Quiz
    1 question

  • Introduction to Qsys and IP Catalog
    11:37
  • Using IP Catalog
    11:14
  • FPGA Block resources and Testing of Integrated cores
    12:39
  • Quartus Primitives / Standard Verilog Primitives
    10:56
  • Introduction to SDC files
    04:34
  • Writing and Adding SDC files into Quartus a Project
    17:27
  • Quiz :
    1 question

  • Preview12:46
  • Free-Running Finite State Machine (FRFSM)
    05:37
  • FRFSM : Coding
    11:46
  • FRFSM : Testbench testing
    05:33
  • FRFSM : Board testing
    07:02
  • Event Driven Finite State Machines
    13:26
  • Event Driven Finite State Machines: Testing using Board
    04:42
  • Multi Event Driven State machine
    07:36
  • Multi Event Driven State machine : Coding
    16:31
  • Dynamic Testbenche
    20:41
  • UART Theory: Tx and Rx
    13:20
  • UART Tx Coding
    16:35
  • Verification on Board and Computer
    08:44
  • UART Rx Coding
    12:48
  • Verification on Board and Computer
    06:16
  • Combining Tx and Rx
    15:30
  • Quiz :
    2 questions

  • Way forward
    04:12
  • Quiz
    2 questions

  • Preview06:15
  • Preview16:05
  • Xilinx Arty S7-25 board by Digilent
    10:13
  • Xilinx Vivado Installation
    05:04
  • Counter Simulation on Xilinx Vivado
    15:15
  • Counter example on Arty S7-25
    13:23
  • Power types, Power banks
    14:21
  • State Machine on Arty S7-25
    15:35
  • Using SPARTAN 7 Block RAM and Verification
    18:21
  • Verilog Tasks and SystemVerilog Assertions
    10:36
  • Tasks and Assertions ; Practical in Vivado
    14:51
  • Register Based Control Systems
    14:36
  • Conclusion
    00:08

Requirements

  • Students having know-how of Digital Logic Design or Digital Electronics or Boolean Algebra will benefit more, as this course assumes prior knowledge of Digital Logic and number systems(Binary, Hexadecimal, Octal, Decimal).
  • At least some knowledge in Engineering or Science is recommended.
  • Student having knowledge in C , C++ or alike languages will benefit more.

Description

This course is designed to make students confident developer of Digital Systems using Verilog and Intel FPGAs(2 different boards and FPGAs). Every aspect is discussed from different angles, so that whole concept becomes clear. This course uses two cheap Intel FPGAs development boards and freely available software(Quartus Lite , ModelSim). Purchasing of boards is absolutely optional. This course can be done without development boards.

Additionally FPGAs and tool chains from other vendors are also introduced briefly.

Who this course is for:

  • Beginners and Hobbyists. In fact, any one who is curious. But keep in mind, this is a technical course.
  • This course gives a practical go through with the FPGA development phases. So, if you have some urgent assignment, and you don't have much background in FPGA development, then may be this course can help you in solving that.
  • Professionals, who already know Microcontrollers, and want to try FPGAs as well.
  • I kept this course as cheap as possible, so that most student can benefit from it.
  • Not suitable for Professional FPGA developers !!!

Instructor

Muhammad Tahir Rana
Sensor (ASIC) developer and Verification Engineer.
Muhammad Tahir Rana
  • 4.1 Instructor Rating
  • 41 Reviews
  • 237 Students
  • 1 Course

Having more than 10 years of industry experience, the author has participated in many projects ranging from Data Processing to Sensor development. The author enjoys Verification more than Designing, so the future courses might be offered on Verification. Authors expertise includes reliability testing, designs for reliability, Digital System Design and Printed Circuit boards.

The author enjoys reading books and arrange charities for poor and homeless.

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