VLSI/FPGA Design P1: CMOS Gates & Arithmetic Datapath

Name: VLSI/FPGA Design P1: CMOS Gates & Arithmetic Datapath
Rating: 5.0 (9 reviews)

Design skyscrapers from bricks

Created bySKY SiliconThink

Last updated 3/2025

English

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What you'll learn

Basic theory of CMOS Gates
Use CMOS transistor to build any Logic Gates
Factors affect cell delay(PVT)
Behavior of Latch and DFF
Deep understanding for Setup/Hold time
Architecture of adder(ripple, carry-select, carry look ahead, tree adders)
Using architecture ideal of adders to optimize your design
Arithmetic operation on real number and any mathematic function
Technic support through Q&A system of Udemy

Course content

4 sections • 19 lectures • 5h 49m total length

Introduction of the whole course(all parts)6:40
Introduce CMOS theory and arithmetic datapaths; master Verilog for digital circuit design and verification with Verilator and GTKWave; cover basic cells, gates, mux, decoder, D flip-flop with resets.
Glossary44:02
Explore essential glossary terms for vlsi/fpga design, including ic, gds2, tapeout, cmos, SoC, IP, EDA tools, RTL, Verilog, SystemVerilog, synthesis, PPA, and DFT concepts.
Conventions2:21
define the course conventions and the meaning of terms like usually, true but for some, and other solutions, clarifying when statements are conditional and when extra information is required.

Silicon and Diode4:54
Explore basic cmos theory, diode behavior, and nmos and pmos transistors; build an inverter to observe input-output response, and define signal transition and delay times in cell-based design.
nMOS & pMOS Transistor12:08
learn how nmos and pmos transistors operate, with four pins (source, drain, gate, body), body tied to ground, and how gate-to-source voltage above threshold enables current flow.
Switch Level Model and Inverter34:50
Learn switch-level CMOS inverter design with nMOS and pMOS, including symbols, zero/one definitions, RC charging/discharging, and how process, voltage, and temperature variations affect timing.
PVT Corners and Quiz10:15
Analyze pvt corners for cmos gates and identify fast, typical, and slow conditions with nmos and pmos. Explore how these corners define valid regions and affect rc wire delays.
Correction of explain for figure of PVT corner3:57
Explain how pt values define a cell delay under a pvt corner by linking the innermost transistor delay to a working condition; note the 1-to-1 forward mapping.

Basic Logic Gates20:47
Tranmition Gate and Tristate20:27
Learn how the data transmission gate uses two inputs, S and the gate, to pass signals to D with high-impedance off states, and why tri-state gates are avoided inside chips.
Factors Affect Cell Delay4:42
Analyze factors affecting cell delay in CMOS gates, including input transition time and output capacitance/loading, and explain how mid-level voltages can trigger both transistors and increase power.
Latch & DFF and Deep Understanding for Setup/Hold Time1:00:16
Explore basic data storage elements, including latch and d-type flip-flop, their data flow through D to Q and clock, and the critical setup and hold time requirements for reliable operation.
Extra 1: Why no D2Q Delay for DFF2:36
Explain why a d flip flop has no d2 delay: after latching, the stored d feeds back, isolating q from d, so q delay is set by the feedback path.
Extra 2: Multi-Driven is not Allowed2:12
Explain why a node driven by two inverters is not allowed when using the same library cells, as unequal driving strengths create an uncertain voltage and mid-level states.
Extra 3: All the Factors That Affect Cell Delay2:13
Identify factors affecting CMOS gate delay, including driving strength, gate size, and input/output loading, and explain how process, voltage, and temperature variations influence delay.

Architecture for Adder & Subtractor and Use the Ideal behind the Arch.1:02:23
Analyze adder and subtractor, then multiplier and divider. Study delay and area differences across architectures and apply carry select and carry lookahead concepts to circuit design.
Architecture for Multiplier and Divider34:42
Examine multiplier and divider architectures for CMOS gates, including partial products, boost encoding, and binary-tree adder designs, plus pipeline and cad ip optimizations.
Arithmetic of Real Number and Any Math. Function17:26
Learn how real numbers are encoded in digital systems using IEEE 754 formats, and how to implement floating-point arithmetic and complex functions with CORDIC and Taylor series.
Promotion: VLSI/FPGA Design Resume Project: 2D DMA Controller with APB+AXI Inf.2:19
Develop a 2d dma controller ip with apb and axi interfaces, a resume-building fpga design project that demonstrates data movement between system addresses in a 2d game demo.

Requirements

Basic knowledge of digital fundamental
Basic C or C++ programing language

Description

Please contact SKY (DM or E-mail to siliconthink@126.com) for special offer of $12.99 USD.

This chapter is foundation of design SOC and FPGA, that's bricks of skyscrapers. Contents in chapter 1:

1: Behavior and characteristics of CMOS gate: switch model, transition time, delay time, PVT corner.

2: Using CMOS gate to build basic logic function gates: NAND, NOR, XOR, mUX.

3: Build arithmetic datapth using basic logic gates: adder, subtractor, multiplier and divider. Learning the HW architecture ideas behind them, and use them to optimize your design.

Once enrolled, you can get technic support through the Q&A system of Udemy.

Let’s cooperate and success.

Note:

This is chapter 1 of the whole Digital IC and FPGA design course.

In the whole course, I will introduce fundamentals of digital IC and FPGA design, with 12+ coding exercises and 3 course projects.

Theory part: MOS transistor -> logic cells -> arithmetic data path -> Verilog language -> common used HW function blocks and architecture -> STA -> on-chip-bus(APB/AHB-Lite/AXI4) -> low power design -> DFT -> SOC(MCU level).

Function blocks and architecture: FSM, pipeline, arbiter, CDC, sync_fifo, async_fifo, ping-pong, pipeline with control, slide window, pipeline hazard and forward path, systolic.

Project: SHA-256 algorithm with simple interface, SHA-256 with APB/AXI interface, 2D DMA controller with APB/AXI interface.

After explaining of each HW architecture, I will give you a coding exercise, with reference code. Coding difficulty will begin from several lines to fifty lines, more than 100 lines, then around 200 lines. While the final big project will be 1000+ lines.

I suppose these should be essential knowledge and skills you need master to enter this area.

I will try my best to explain what-> how-> why and encourage you to do it better in this course.

Please browse to my homepage on Udemy to obtain information about each chapter of this course.

Who this course is for:

Senior undergraduate students of EE or higher
IC design/verification engineers with 0~2 years’ experience

VLSI/FPGA Design P1: CMOS Gates & Arithmetic Datapath

What you'll learn

Explore related topics

Course content

Introduction3 lectures • 53min

Basic CMOS Theory5 lectures • 1hr 6min

Basic Logic Gates7 lectures • 1hr 53min

Arithmetic Datapath4 lectures • 1hr 57min

Requirements

Description

Who this course is for: