Digital Design with SystemVerilog HDL + Introduction to UVM

Learn the Modelsim workflow from installation to running a simple testbench, verify design outputs, and practice a hello world design to build foundational skills for future simulations.

Download and install ModelSim from the official page by selecting the latest release and Windows installer. Complete the setup with default options and open ModelSim to run your first simulation.

Create a folder with underscores (no spaces), place hello_world and hello_world_TB, then open ModelSim, compile, and run the testbench to see hello world in the transcript.

Learn how to run simulations using a provided template and a test bench, create folders for each assignment, use Notepad++ and save files as .csv with names matching their modules.

Explore multiplexers in SystemVerilog by comparing data-flow and behavioral designs for 2-to-1 and 4-to-1 muxes, and simulate the 4-to-1 mux in Modelsim.

Examine the 4-to-1 multiplexer specification and how output q follows the selected input x0–x3 via select lines s1 and s0, with an accompanying truth table and example mappings.

Design a 2 to 1 multiplexer in dataflow style, linking inputs A, B and select S to output Q with a dataflow assign statement, and show the equivalent ternary implementation.

Design a 4-to-1 multiplexer using the dataflow style, mapping the behavioral equation and truth table for s1 and s0 to an assign-based logic expression and the ternary form.

Design a full adder in systemverilog using dataflow, with inputs A, B and sin, outputs sum and cout; implement sum and cout with assign statements.

Design a 2:1 multiplexer in behavioral style. Describe q equals a when s is 0 and q equals b when s is 1 using if-else or case statements.

Design and implement a 4:1 multiplexer in SystemVerilog HDL using if-else and case statements, driven by select inputs S1 and S0 to route x0–x3 to q.

Run a 4-to-1 multiplexer simulation in Modelsim by compiling the testbench, open the waveform to view DUT signals, add wave, and zoom as needed to verify the output q.

Present the full adder behavior using an always_comb block and a single assignment {cout, sum} = a + b + cin, to express arithmetic intent beyond gate-level logic.

Learn how to use begin and end in SystemVerilog to group multiple statements, similar to curly braces in other languages, and know when to wrap statements for multi-line blocks.

Explore assign for continuous single-line combinational logic and always_comb for multi-line expressions in SystemVerilog, including conditionals such as if or case and the use of temporary variables.

Discover how SystemVerilog replaces Verilog's wire and reg with logic, enabling assignments in both continuous and procedural contexts. Understand when wire is required for multiple drivers and tristate buses.

Explore structural design by instantiating and connecting modules, wiring 2-to-1 and 4-to-1 multiplexers into a 16-bit encoder, implemented in SystemVerilog and verified with Modelsim, highlighting modular, reusable architectures.

Design a 4:1 multiplexer by composing two 2:1 mux blocks into n1 and n2, then a final mux selects between them with s1 and s0 to drive q.

Learn how a four-bit priority encoder selects the highest priority active input, outputs its binary position on q1 q0, and asserts a valid signal.

Build a 16 bit priority encoder using a 4 to 1 multiplexer, where the highest priority input wins; the example with A5 and A11 yields 1011.

Explore the 16-bit priority encoder architecture built from four 4-to-2 encoders and a multiplexer, selecting the highest priority group and inside-group input to produce a 4-bit output.

Demonstrates running a 16-bit priority encoder example with inputs A6 and A9, showing the first-layer four-to-two encoders and a top encoder selecting A9, yielding binary nine.

Design a 16-bit priority encoder in SystemVerilog. Group A0–A15 into four blocks, each with a 4-to-2 encoder, then select the winning group to output V, q3, q2, q1, q0.

Simulate a 16-bit priority encoder in Modelsim by compiling the encoder and testbench files, then verify that bit 13 yields output 1101, confirming priority encoding.

Design a four-bit ripple carry adder using four full adders and carries C1, C2, and C3, producing carry out and illustrating ripple behavior with 7 plus 8 equals 15.

Design an ALU in SystemVerilog by defining inputs, outputs, bit width, and carry flags, using bitwise, reduction, shift, and relational operators; simulate tests in ModelSim to verify the spec.

The ALU is the processor's digital circuit that performs arithmetic and logical operations, a chart for and, or, complement, rotates through carry, add with carry, subtract with borrow, and move.

Explore how buses turn multiple signals into a single vector in SystemVerilog, using a 4-to-1 multiplexer with byte-wide inputs x0 through x3 and a two-bit select s.

Explore bitwise operations on individual bits of binary numbers, including or, and, and xor across buses; a result bit is one when an odd number of input bits are one.

Explore reduction operators that collapse a multi-bit vector to one bit, using or for any one bit, nand for any zero, and xor for parity checks to form even parity.

Explore SystemVerilog shift operators that move bits in a vector, with logical shifts filling zeros and arithmetic right shifts preserving sign, examples showing multiplication by four and division by two.

Explore relational and equality operators in Verilog and SystemVerilog, and learn how they drive decision making in the ALU and finite state machines.

Design alu in systemverilog for 8-bit a and b. Use a 3-bit opcode to perform and, or, not, rotate with carry, add, subtract with borrow, or move, producing y.

Analyze the ALU simulation waveform to verify the selected operation, inputs, and outputs cycle by cycle. Compare with the operations table to confirm bitwise, addition, and subtraction behavior as intended.

Explore flip flops and registers to store data across clock cycles, compare blocking and non-blocking assignments, and design and simulate an eight-bit register and a sixteen-bit counter in Modelsim.

Explore the D flip-flop as a fundamental sequential element that captures data on a rising clock edge, holds q, and clears q to zero with an active-low reset.

Store binary data with a register built from flip flops; an eight-bit register uses eight flip flops in parallel, SystemVerilog widens the input and the output q into a vector.

Explore blocking and non-blocking assignments in SystemVerilog, comparing immediate versus end-of-time-step updates and their roles in combinational versus sequential logic with practical examples.

Compare blocking and non-blocking assignments using a flip-flop example to show sequential updates on the clock edge for blocking, versus parallel updates at the end of the cycle for non-blocking.

Operate the 8-bit register on the rising clock edge with an asynchronous reset and four prioritized operations: reset, load, increment, rotate right; otherwise, hold the value.

Design an 8-bit register in SystemVerilog with clock, an active-low reset, data input D and output Q. Enforce a priority: load, inc, rotateright (circular right shift), else hold.

Simulate an 8-bit register in model sim; reset n asynchronously clears to zero immediately. Demonstrate load of input D when high and priority of increment over rotateright when both active.

Understand the specifications of a 16-bit counter with clock, reset n, and increment inputs and output Q, split into two 8-bit blocks where lsb reaches all ones before msb increments.

Reuse the eight-bit register to build two eight-bit counters, concatenate them into a 16-bit counter, and have the high counter increment only when low counter overflows via the global increment.

Design a 16-bit counter from two 8-bit registers. Low byte increments on clock and generates a carry when full, advancing high byte; q is concatenation of high and low bytes.

Simulate the 16-bit counter in Modelsim and view the waveform in hexadecimal or decimal to read counts clearly, noticing wraparound when the lower eight bits reach f-f.

For classic Verilog, the generic always block covers both combinational and sequential logic with manual sensitivity lists, while SystemVerilog adds always comb and always flip flop to reduce mistakes.

Explore the fifo concept as a data storage structure that balances data flow between components at different speeds, and clock domains, with first in, first out buffering for streaming data.

Explore how a fifo uses a width-depth memory with push and read pointers in a circular buffer, where empty and full are determined by last operation being read or write.

Implement a parameterized fifo with first-in, first-out behavior using address width to set depth (2^address width) and data width for word size, with read and write pointers and full/empty flags.

Watch a fifo simulation push data into empty memory, later drain it with pop operations, and observe pointer equality and flags—empty, full, and last operation—to enforce first-in, first-out.

Explore finite state machines, featuring Mealy and Moore models, and design a 1-1-0-1 sequence detector. Compare Mealy and Moore designs through simulation to apply state machine thinking to digital design.

Finite state machines describe systems in a single state at a time and change state via inputs; they cycle a finite set of states such as red, green, and yellow.

Compare Mealy and Moore finite state machines: Mealy outputs depend on state and input for immediate changes; Moore outputs depend only on state and update on a clock edge.

Explore a 1101 sequence detector built as a finite state machine that detects overlapping 1101 patterns in a serial input. Compare Mealy and Moore outputs through immediate versus next-clock responses.

Design a mealy finite state machine that detects the 1101 sequence in a serial input stream, outputting one on full detection and including overlaps.

Design a Mealy state machine that detects a bit sequence using clock, reset n, and serial input x, with output z when detection occurs, using S0–S3 states and overlap handling.

simulate a mealy fsm sequence detector for 1101 in ModelSim, where x is input and z is output; after reset, z asserts on final input in the same clock cycle.

Explore Moore FSM for detecting the 1101 sequence, adapting from the Mealy version, listing states S0–S4, assigning fixed outputs, and defining state transitions and overlap.

Design a Moore finite state machine for a sequence detector with states S0 through S4, next state logic in a case statement, and z asserting on detection, supporting overlap.

Observe a Moore FSM simulation of a 1101 sequence detector in ModelSim; X is the serial input and Z the output, with an active low reset, synchronized to the clock.

Design a traffic light controller as a finite state machine with clock input and active low reset. Cycle red 20, green 15, yellow 5, via a five-bit timer.

Explore memory in digital systems, compare ROM and RAM, and design and simulate a single-port RAM in SystemVerilog using ModelSim, verifying read and write operations.

Memory uses a digital circuit to store data bits as an array of cells with addresses. Depth and address width define capacity, and memory supports read and write operations.

Explore ROM and RAM, including fixed ROM for programs and lookup tables, and volatile RAM for temporary data; compare SRAM for fast caches with DRAM main memory.

Highlight the speed, size, and power cost of registers versus memory. Registers use flip flops for fast, small storage, while memory uses SRAM/DRAM for large, dense, slower storage.

Master single-port ram: one access port per clock, with din, dout, address, and write enable, eight-bit width, depth 16, address width 4, enabling read or write per cycle.

Design a synchronous single-port RAM with parameterized address and data widths, exposing a memory array, write enable control, and read updates dout with the stored value.

Examine a single-port ram simulation by viewing the waveform and memory cells, observing writes with high write enable and reads with low enable at clock edges.

Explore a simple serial system with a transmitter and receiver, using handshake signals wr ready, dt valid, and dt finish to ensure synchronized, reliable data transfers on the dt line.

Explore the tx architecture, where rom memory feeds a shift register to the tx line. A state machine loads, shifts, increments address while monitoring rx ready, tx valid, tx finish.

Design a parameterized tx rom with data width and address width that stores transmit data in a synchronous read-only memory, loaded from memory.list and read signal active on clock.

Trace the TX block state machine from idle after reset through r x ready, then load register, shift with tx valid, increment address, and finish after all data is sent.

Designs the tx state machine as the transmitter control unit, sequencing idle to rx, ready, load register, shift, increment address, and tx finish, with memory reads and a three-bit counter.

Design the top level tx block that serializes memory data into tx data via a shift register and address counter, using rx ready handshake and a state machine.

Reset TX block, initialize registers, set address to zero, clear shift register; wait for rx ready, load data, shift eight bits LSB first, increment address, TX finish after last byte.

Explain the rx architecture that receives data from the dt block, featuring a shift register, ram, an address register, and a state machine coordinating shifting and writing with rx-ready handshakes.

Design a parameterized synchronous single-port ram in SystemVerilog that writes data on clock with write enable and reads stored bytes, enabling memory for bytes reconstructed from a serial data stream.

Starts in idle after reset with ready high; dt valid goes high, shifts bits into the register, writes the byte to ram, and increments the address until the last byte.

Controls the receiver with a finite state machine. The machine cycles idle, shift, ram write, increment address, and rx finish, coordinating clock, reset, and dt valid to manage rx ready.

Capture serial data from the transmitter using a shift register. Store bytes in an eight-by-four ram via an rx state machine and manage handshake with tx valid and rx finish.

Simulate rx block after reset: initialize registers, rx ready low when tx valid goes high, shift bits lsb to msb, store bytes to memory, finish when data are written.

Connect the transmitter and receiver to form a complete serial data link. Exchange data through a handshake using Tx data, Tx valid, Rx ready, and Tx finish and Rx finish.

Shows a tx rx serial simulation where the transmitter waits for rx ready, asserts tx valid, and transmits four bytes into memory, with finish signals confirming reception and data integrity.

Explore the universal verification methodology (UVM) through a coffee order analogy, detailing the core components like DUT, interface, transaction item, sequencer, driver, monitor, scoreboard, agent, environment, and test structure.

Verify a coffee machine system that maps size, milk, and foam inputs to espresso, latte, or cappuccino within one clock cycle. Explore testbench design that verifies behavior over implementation.

Define the interface as the signal set connecting the testbench to the DUT, including clock synchronization and signals for size (0 small, 1 large), milk, foam, and coffee_type.

Organize your UVM testbench with the coffee package by grouping transaction, sequencer, driver, monitor, scoreboard, and environment, and use imports and UVM macros to register with the factory.

The transaction class models a coffee order with fields for size, milk, foam, and coffee type, with a foam implies milk constraint. The sequencer delivers to the driver, managing flow.

Receive a virtual interface via the UVM configuration database and drive the transaction fields onto the DUT interface. Publish observations through an analysis port and pair outputs with previous inputs.

The scoreboard verifies the dut by matching size, milk, and foam to the expected coffee type, logging results or errors, while the agent bundles sequencer, driver, and monitor.

Outline environment as the top-level container linking the coffee agent and scoreboard, where the agent generates stimulus via the sequencer, driver, and monitor, and the sequence issues twenty coffee orders.

Define test as the topmost UVM component, build the coffee environment with an agent, scoreboard, and coffee sequence to generate orders, then run on the sequencer and raise an objection.

Explore a SystemVerilog UVM test bench that wires the coffee machine dut to an interface with a 5 ns clock, using a sequence, sequencer, driver, monitor, and scoreboard for validation.

Build and verify a complete UVM verification environment around the coffee machine DUT. See how the interface, transaction, sequencer, driver, monitor, scoreboard, agent, and environment drive order validation and outcomes.