Digital Design with SystemVerilog HDL + Introduction to UVM

Download and install ModelSim from the official page by selecting the latest release and Windows installer. Complete the setup with default options and open ModelSim to run your first simulation.

Create a folder with underscores (no spaces), place hello_world and hello_world_TB, then open ModelSim, compile, and run the testbench to see hello world in the transcript.

Design a 2 to 1 multiplexer in dataflow style, linking inputs A, B and select S to output Q with a dataflow assign statement, and show the equivalent ternary implementation.

Design a 4-to-1 multiplexer using the dataflow style, mapping the behavioral equation and truth table for s1 and s0 to an assign-based logic expression and the ternary form.

Explore the 16-bit priority encoder architecture built from four 4-to-2 encoders and a multiplexer, selecting the highest priority group and inside-group input to produce a 4-bit output.

Demonstrates running a 16-bit priority encoder example with inputs A6 and A9, showing the first-layer four-to-two encoders and a top encoder selecting A9, yielding binary nine.

Design a 16-bit priority encoder in SystemVerilog. Group A0–A15 into four blocks, each with a 4-to-2 encoder, then select the winning group to output V, q3, q2, q1, q0.

The ALU is the processor's digital circuit that performs arithmetic and logical operations, a chart for and, or, complement, rotates through carry, add with carry, subtract with borrow, and move.

Explore bitwise operations on individual bits of binary numbers, including or, and, and xor across buses; a result bit is one when an odd number of input bits are one.

Analyze the ALU simulation waveform to verify the selected operation, inputs, and outputs cycle by cycle. Compare with the operations table to confirm bitwise, addition, and subtraction behavior as intended.

Explore flip flops and registers to store data across clock cycles, compare blocking and non-blocking assignments, and design and simulate an eight-bit register and a sixteen-bit counter in Modelsim.

Compare blocking and non-blocking assignments using a flip-flop example to show sequential updates on the clock edge for blocking, versus parallel updates at the end of the cycle for non-blocking.

Implement a parameterized fifo with first-in, first-out behavior using address width to set depth (2^address width) and data width for word size, with read and write pointers and full/empty flags.

Design a Mealy state machine that detects a bit sequence using clock, reset n, and serial input x, with output z when detection occurs, using S0–S3 states and overlap handling.

Design a traffic light controller as a finite state machine with clock input and active low reset. Cycle red 20, green 15, yellow 5, via a five-bit timer.

Explore ROM and RAM, including fixed ROM for programs and lookup tables, and volatile RAM for temporary data; compare SRAM for fast caches with DRAM main memory.

Master single-port ram: one access port per clock, with din, dout, address, and write enable, eight-bit width, depth 16, address width 4, enabling read or write per cycle.

Explore the tx architecture, where rom memory feeds a shift register to the tx line. A state machine loads, shifts, increments address while monitoring rx ready, tx valid, tx finish.

Starts in idle after reset with ready high; dt valid goes high, shifts bits into the register, writes the byte to ram, and increments the address until the last byte.

Controls the receiver with a finite state machine. The machine cycles idle, shift, ram write, increment address, and rx finish, coordinating clock, reset, and dt valid to manage rx ready.

Receive a virtual interface via the UVM configuration database and drive the transaction fields onto the DUT interface. Publish observations through an analysis port and pair outputs with previous inputs.

Explore a SystemVerilog UVM test bench that wires the coffee machine dut to an interface with a 5 ns clock, using a sequence, sequencer, driver, monitor, and scoreboard for validation.