Digital Design from Scratch
4.8 (17 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
125 students enrolled

Digital Design from Scratch

Using VHDL in FPGAs from the ground up
Bestseller
4.8 (17 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
125 students enrolled
Created by Blaine Readler
Last updated 4/2020
English
English [Auto]
Current price: $13.99 Original price: $19.99 Discount: 30% off
5 hours left at this price!
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This course includes
  • 7 hours on-demand video
  • 32 downloadable resources
  • Full lifetime access
  • Access on mobile and TV
  • Assignments
  • Certificate of Completion
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What you'll learn
  • After completing the course, the beginning student will be able to create working logic programs that run on free simulation software and low-cost FPGA development boards.
Course content
Expand all 32 lectures 07:12:40
+ Fundamentals
8 lectures 56:11

An introduction to the concept of digital versus analog.

Preview 07:16
These are exercises that cover the first four lectures, providing an opportunity for participation learning.
Exercises for lectures 1.1-1.4
1 question
1.5: enabled latches, series operations, and rising-edge pulses
08:01
1.6: process and conditional statements, clocked registers
07:26
1.7: register-to-register transfers, hold/setup time
06:54
1.8: elsif, enabled set/reset flop, propogation delays
06:59
Practice exercises for lectures 1.5 through 1.8
Assignement 2: Exercises for lectures 1.5-1.8
1 question
+ Functional Design Components
8 lectures 01:09:46
2.1: binary and hexadecimal numbers
09:55
2.2: shift registers, counters, vectors, and 1k vs. 1K
09:22
2.3: counter in the traffic light application, edge and terminal count detect.
11:47
2.4: coding from timing diagrams
09:15
These are exercises that cover the first four lectures of Section 2, providing an opportunity for participation learning.
Exercises for lectures 2.1-2.4
1 question
2.5: introduction to state machines
07:10
2.6: case statements
05:14
2.7: state machines, case statements, and the traffic example
07:28
2.8: coding the simple traffic state machine
09:35
These are exercises that cover the last four lectures of Section Two, providing an opportunity for participation learning.
Exercises for lectures 2.5-2.8
1 question
+ FPGAs, VHDL, and simulation
8 lectures 01:21:59
3.1: introduction to FPGAs
10:19
3.2: VHDL head-on, text editors
06:01
3.3: entities and architectures, vector types, and VHDL libraries
11:56
3.4: modular design, debounce, falling-edge detection
11:43
These are exercises that cover the first four lectures of Section Three, providing an opportunity for participation learning.
Exercises for lectures 3.1-3.4
1 question
3.5: introduction to simulation
06:43
3.6: simulation testbench, creatiing stimulus
12:24
3.7: introduction to Modelsim, constants, stalling process statements
08:42
3.8: using Modelsim
14:11
These are exercises that cover the last four lectures of Section Three, providing an opportunity for participation learning.
Exercises for lectures 3.5-3.8
1 question
+ Practical FPGA Elements
8 lectures 01:42:12
4.1: single and dual-port memories
09:23
4.2: arrays and while loops
13:41
4.3: inferred memories, coded dual-port memory, shared bus RAM, tri-state buffer
08:11
4.4: FIFOs
12:44
These are exercises that cover the first four lectures of Section Four, providing an opportunity for participation learning.
Exercises for lectures 4.1-4.4
1 question
4.5: Avalon and AXI memory-mapped buses
19:02
4.6: serial interfaces, RS232, UARTs
13:57
4.7: I2C, SPI, clocks and timing
16:26
4.8: introduction to DSP
08:48
These are exercises that cover the last four lectures of Section Four, providing an opportunity for participation learning.
Exercises for lectures 4.5-4.8
1 question
Requirements
  • A rudimentary understanding of algebra is helpful, but not necessary.
Description

VHDL is a powerful programming language for developing FPGAs, but is useless without an in-depth understanding of digital design. This course provides the student a comprehensive working knowledge of both of these in parallel. VHDL describes digital logic, and, as such, is an ideal vehicle for developing a deep understanding of the functional power available in modern FPGA devices.

Who this course is for:
  • Entry level students interested in developing programs for FPGAs.
  • Technicians and engineers who would like to learn VHDL (an FPGA programming language).