Digital Design from Scratch

Name: Digital Design from Scratch
Rating: 4.5 (86 reviews)

Using VHDL in FPGAs from the ground up

Highest Rated

Created byBlaine Readler

Last updated 8/2022

English

English [Auto],

What you'll learn

Digital design basics, including logic gates, binary/hexadecimal numbers, registers, shift registers, counters, timing diagrams, propagation/setup/hold timing
VHDL language basics, including VHDL file formats/libraries, coding logic equations, conditional statements, arrays, timing constraints
Coding, including case statements, state machines, coding from timing diagrams, while-loops, standard/unsigned types, VHDL components (modules), simulation
Practical examples: memories (inferred/dual port), FIFOs, memory-mapped buses, serial interfaces (RS232, UARTs, I2C, SPI), DSP, PLLs, Manchester/8B10B encoding

Course content

5 sections • 33 lectures • 7h 28m total length

1.1: Introduction7:16
An introduction to the concept of digital versus analog.
1.2: Boolean logic gates, binary state, and timing diagrams7:46
1.3: traffic light example, coding Boolean equations4:59
1.4: the latch6:50
Explore how a latch acts as a memory element via set-reset feedback, sustaining output after inputs change. Apply boolean expressions and or gates to traffic lights logic.
Exercises for lectures 1.1-1.4
1.5: enabled latches, series operations, and rising-edge pulses8:01
Explore enabled latches and series d flip-flops to implement time-stepped, rising-edge pulse operations that reset a traffic light after a four-second timer.
1.6: process and conditional statements, clocked registers7:26
Examine clocked registers and latches via a rising-edge D flop in VHDL. Explore conditional when statements, sensitivity lists, and the process structure that implements a D flop.
1.7: register-to-register transfers, hold/setup time6:54
Explore register-to-register transfers by clocking outputs into inputs, learn about setup and hold times, and analyze set-reset latches and set clock latches in FPGA clocked designs.
1.8: elsif, enabled set/reset flop, propogation delays6:59
Assignement 2: Exercises for lectures 1.5-1.8

2.1: binary and hexadecimal numbers9:55
Explore binary arithmetic and representations, group four-bit binary values to represent numbers, identify the least and most significant bits, and learn hex notation with 0x and a through f.
2.2: shift registers, counters, vectors, and 1k vs. 1K9:22
Explore shift registers, counters, and vectors, and distinguish 1k from 1K in binary data. Learn to count with six-bit counters, use signal buses, and implement simple addition in HDL.
2.3: counter in the traffic light application, edge and terminal count detect.11:47
2.4: coding from timing diagrams9:15
Exercises for lectures 2.1-2.4
2.5: introduction to state machines7:10
2.6: case statements5:14
2.7: state machines, case statements, and the traffic example7:28
Explore how to implement a traffic light controller as a state machine using a case statement, with a multi-purpose counter timer managing idle, yellow, and green phases.
2.8: coding the simple traffic state machine9:35
Exercises for lectures 2.5-2.8

3.1: introduction to FPGAs10:19
3.2: VHDL head-on, text editors6:01
Learn how to write VHDL code with plain text files and a text editor, covering header and entity declarations, architecture, and editor features like syntax highlighting and auto indentation.
3.3: entities and architectures, vector types, and VHDL libraries11:56
Explore the structure of a VHDL file by examining entities, architectures, port declarations, and vector signals. Learn how unsigned arithmetic, type conversions, and HDL libraries enable practical timer counter designs.
3.4: modular design, debounce, falling-edge detection11:43
Learn modular design by using a pulse generator and toggle block to debounce a push button and implement falling-edge detection on an FPGA, with hierarchical component instantiation.
Exercises for lectures 3.1-3.4
3.5: introduction to simulation6:43
3.6: simulation testbench, creatiing stimulus12:24
Create a simulation testbench that generates stimulus signals to drive the FPGA design, instantiate the top level component, and produce a 10 MHz clock for verification.
3.7: introduction to Modelsim, constants, stalling process statements8:42
3.8: using Modelsim14:11
Learn to use ModelSim with GUI and script workflow, set up folders, add source files, compile, and simulate to generate waveforms from test benches.
Exercises for lectures 3.5-3.8

Requirements

A rudimentary understanding of algebra is helpful, but not necessary.

Description

VHDL is a powerful programming language for developing FPGAs, but is useless without an in-depth understanding of digital design. This course provides the student a comprehensive working knowledge of both of these in parallel. VHDL describes digital logic, and, as such, is an ideal vehicle for developing a deep understanding of the functional power available in modern FPGA devices.

Who this course is for:

Entry level students interested in developing programs for FPGAs.
Technicians and engineers who would like to learn VHDL (an FPGA programming language).

Digital Design from Scratch

What you'll learn

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Course content

Fundamentals8 lectures • 56min

Functional Design Components8 lectures • 1hr 10min

FPGAs, VHDL, and simulation8 lectures • 1hr 22min

Practical FPGA Elements8 lectures • 1hr 42min

Bonus: clock recovery in serial interfaces1 lecture • 10min

Requirements

Description

Who this course is for: