Design Verification with SystemVerilog/UVM
What you'll learn
- Module level verification using SystemVerilog and UVM library.
- Build agents in SystemVerilog/UVM to drive and monitor communication interfaces.
- Build the model of the registers using UVM and connect it to the APB interface in order to let UVM perform its automatic checks on the register accesses.
- Build the functional model of a Device Under Test (DUT) and use it to predict the correct response expected from the DUT.
- Build a scoreboard to verify automatically all the expected outputs of a DUT.
- Build the coverage model and all the logic necessary to collect that coverage.
- Build random tests to verify all the features of a DUT.
- Learn how to deal with synchronization issues in the model.
Requirements
- You need to have a basic understanding of digital integrated circuits and how they are modeled in a HDL language like Verilog.
- There is no hard requirement for your to know SystemVerilog but prior OOP and Verilog knowledge is required.
Description
Master UVM Library & Create a Verification Environment: Comprehensive Course Overview
In this course, you'll delve into two crucial areas:
UVM Library: Uncover all its features, secrets, and how they can be applied effectively in verification environments.
Verification Environment Creation: Learn the step-by-step process of building a robust verification environment from the ground up using UVM.
Course Objectives:
Throughout this course, we'll guide you through the development of a verification environment, meticulously designed using the UVM library. Each tutorial will introduce new functionalities, demonstrating the UVM features necessary for each phase of our comprehensive project.
We'll leverage the EDA Playground platform to develop our verification environment. By the end of the course, our final project will encompass over 5000 lines of code, providing a substantial showcase of your acquired skills and knowledge.
By the end of this course, you will master:
Building UVM agents and understanding their roles
Modeling design registers using the UVM library
Setting up a Device Under Test (DUT) within a verification environment
Verifying the outputs of a DUT to ensure accuracy and functionality
Implementing functional coverage in SystemVerilog to achieve thorough verification
Writing and executing random tests to cover a wide range of scenarios
Employing advanced debugging techniques to identify and resolve issues
Exploring and utilizing hidden features of the UVM library to enhance your projects
The skills you gain from this course will not only prepare you for entry or junior-level verification engineer job interviews but will also ensure you are productive and effective from day one in your new role.
Who this course is for:
- Students and engineers who want to learn how to do module level verification using SystemVerilog language and UVM library.
Instructor
- 4.7 Instructor Rating
- 167 Reviews
- 3,950 Students
- 1 Course
I am a senior verification engineer with around 20 years experience in ASIC functional verification.
I have contributed to the successful completion of projects ranging from start-ups to well established companies.
Professional Experience:
- 20 years experience as a functional verification engineer using 'e' language and SystemVerilog
Technical Specialties:
- Master of Engineering in Microelectronics
- Functional verification at block level and system level using constrained random verification
- Verification components development
- Programming Languages: 'e', SystemVerilog, Java, Kotlin, Python, C#, Swift
- Verification Methodologies: UVM, eRM
- EDA Tools: Incisive (Cadence), Questa (Siemens), VCS (Synopsys)