Udemy
    •  
    •  
    •  
    •  
    •  
    •  
    •  
    •  
Subscribe
Turn what you know into an opportunity and reach millions around the world.
Learn More
Your cart is empty.
Keep shopping
Design for Test (DFT) : From Zero to Hero
Rating: 4.0 out of 5(11 ratings)
260 students

Design for Test (DFT) : From Zero to Hero

Master Scan Chains, Fault Models, & the Complete DFT Flow with Synopsys Tools Includes Hands-On Labs and TCL Constraints
Created byElectronics Zone
Last updated 2/2026
English
English [Auto],

What you'll learn

  • Understand the difference between functional test and manufacturing test
  • Model physical defects using stuck-at, bridging, and transistor fault models
  • Master controllability and observability—the core concepts of testability
  • Design scan chains by converting normal flip-flops to scan flip-flops
  • Implement the three-phase scan process: Shift In, Capture, and Shift Out
  • Apply essential DFT guidelines to make designs scan-ready
  • Prepare RTL for DFT by adding scan ports and multiplexing clocks and resets
  • Run test-ready compile using Synopsys tools
  • Configure scan chains with TCL constraints for clock mixing, chain length, and scan style
  • Define DFT signals using set_dft_signal for clocks, resets, enables, and test modes
  • Create test protocols and run pre-DFT design rule checks
  • Preview and insert scan chains with insert_dft
  • Perform post-DFT optimization and final DRC with coverage estimation
  • Interpret test coverage reports and fault classifications
  • Complete hands-on labs to edit RTL, write TCL constraints, and generate a fully scanned netlist

Course content

1 section • 10 lectures • 3h 36m total length

  • Introduction & Manufacturing Test Vs Functional Test19:56

    Explore design for test, scan chains, and ATBG for manufacturing test. Differentiate functional from manufacturing test, and introduce fault models like stuck-at and bridging for test coverage.

  • Fault Models16:06

    Examine stuck-at faults, bridging faults, and transistor faults in design for test (DFT); learn to model defects, generate test patterns, and understand their impact on modern chips.

  • Controllability and Observability17:50

    Explore controllability and observability in digital circuits, illustrate the control/observe trade-off with a three-gate example, and introduce scan chains that turn flip-flops into internal control and observation points for testability.

  • Scan Chains20:08

    Replace every flip-flop with a scan flip-flop and connect them in a scan chain to enable controllability and observability via scan input and scan output, with shift-in, capture, and shift-out.

  • ShiftIn & Capture & ShiftOut28:19

    Explore design for test fundamentals with scan testing, including shift-in, capture, and shift-out phases, fan-in cones, and nine essential guidelines for reliable testing.

  • DFT Flow15:47

    Navigate the full dft flow from rtl preparation to scan insertion, defining dft constraints and test protocols. Perform pre- and post-drc checks, generate the scanned netlist, and prep for handoff.

  • DFT Constraints32:01

    Learn to configure scan chains with set-scan-configuration, define DFT signals, and run pre-DFT and post-DFT checks to optimize test coverage from zero to hero.

  • Lab_DFT_149:59

    Apply design-for-test concepts by preparing RTL with scan ports and muxed clocks and resets, generating Verilog netlists. Run dftscript.tcl on Linux to perform pre and post DFT checks.

  • Lab_DFT_216:16

    Run the dftscript.tcl with snoops on Linux, inspect and fix DRC violations in RTL and constraints, and validate master, generated, and scan clocks with high test coverage.

  • Assignment_DFT_10:04

Requirements

  • Basic knowledge of digital logic design (gates, flip-flops, combinational logic) & TCL Scripting
  • Familiarity with a hardware description language like Verilog or VHDL (you should be able to read and understand basic RTL)
  • Some exposure to synthesis concepts is helpful but not required
  • No prior DFT knowledge needed—we start from the beginning
  • For the labs, access to Synopsys DFT Compiler is recommended but not mandatory; the concepts are taught independent of specific tool versions

Description

Unlock the secrets of semiconductor testing and become a DFT expert! USE PROMO PAY_13

You've designed a brilliant chip. You've simulated every function and checked every timing path. You send it to fabrication, get the chips back... and half of them don't work. The design was perfect, but the silicon had physical defects. How do you find those defective chips before they reach your customers? The answer is Design for Test, or DFT.

This course is your complete guide to DFT, taking you from absolute beginner to someone who can confidently insert scan chains, run design rule checks, and achieve industry-standard test coverage. No prior DFT knowledge is required—just a solid understanding of digital logic design.

We start with the fundamentals: What are physical defects? How do we model them using stuck-at, bridging, and transistor faults? You'll learn the critical concepts of controllability and observability—why some nodes are easy to test and others are nearly impossible without special techniques.

Then we dive into the heart of DFT: scan chains. You'll understand exactly how a scan flip-flop works, how they're connected into chains, and how the three-phase process of Shift In, Capture, and Shift Out gives us complete control over every internal node. We'll cover the timing and area trade-offs and the essential design guidelines that make scan possible.

But this course isn't just theory. It's packed with practical, real-world knowledge. You'll learn the complete DFT compiler flow used by professional engineers every day. We'll walk through each step:

  • RTL preparation for DFT—adding scan ports and multiplexing clocks and resets

  • Test-ready compile with Synopsys tools

  • Configuring scan chains using TCL constraints

  • Defining DFT signals with set_dft_signal

  • Creating test protocols and running pre-DFT design rule checks

  • Previewing and inserting scan chains with insert_dft

  • Post-DFT optimization and final DRC

  • Test coverage analysis and interpreting results

Hands-On Learning:

This course includes two comprehensive labs and a final assignment where you'll apply everything you learn. You'll edit RTL to make it DFT-compatible, write real TCL constraints to configure scan architecture, and use Synopsys DFT Compiler to insert scan chains into an actual design. By the end, you'll have a complete scanned netlist and a test coverage report—exactly what you'd deliver in a real industry project.

Whether you're a student wanting to break into the semiconductor industry, a verification engineer looking to expand your skills, or an experienced designer who's never quite understood DFT, this course is for you. The chips we design go into cars, medical devices, and space missions. They have to work. DFT is how we make sure they do.

Enroll today and master Design for Test!

Who this course is for:

  • Engineering students who want to break into the semiconductor industry and need practical DFT knowledge
  • Fresh graduates starting their careers in VLSI, ASIC, or FPGA design who want to stand out from the competition
  • Digital design engineers who create RTL but have never fully understood what happens during DFT insertion
  • Verification engineers who want to understand the test structures they're verifying
  • Experienced professionals moving into DFT roles or wanting to fill gaps in their knowledge
  • Anyone involved in chip design who wants to understand how manufacturing test actually works and why DFT is essential

Report abuse