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IT & SoftwareHardwareFPGA

Building Custom AXI Interface Peripherals for ZYNQ Devices

All about AXI Slave Lite and AXI Stream Interface
Rating: 4.6 out of 54.6 (25 ratings)
269 students
Created by Kumar Khandagle
Last updated 11/2021
English
English [Auto]

What you'll learn

  • Building custom AXI Slave Lite Interface
  • Handling Interrupts with Custom AXI Slave Lite Interface
  • Creating Custom AXI Stream Interface with Vivado Template
  • Building Custom AXI Stream Interface with Verilog RTL
  • Writing Drivers for Custom AXI Interface
  • Interfacing of Custom AXI Interface with Zynq devices

Requirements

  • Fundamentals of Xilinx Drivers and Embedded Design Flow

Description

As system complexities are growing day by day, the Zynq device alone is incapable of providing the same performance and the Pure RTL module or Programmable logic (PL) needs to be integrated along with the Zynq. As Zynq works with Advanced Extensible Peripheral (AXI), it becomes mandatory for FPGA engineers to gain a fundamental understanding of adding AXI Interface to the Verilog RTL. The AXI4 offers different variants to fit diverse application needs. Understanding of the simpler variants such as AXI Lite and AXI Stream Interface lays a foundation for building an understanding of the complex AXI4 variant such as AXI Full.   

This course focuses on the usage of the Vivado IP Integrator and Vivado RTL integration for building the custom AXI interface for pure Verilog modules. There are four ways to achieve the addition of the AXI interface to the Verilog RTL viz. Using Vivado IP Packager, Vivado RTL Integration, Using System Generator, Using Vivado HLS. The course discusses two methodologies viz. Vivado IP Packager and Vivado RTL Integration in details with a simple example along with the demonstration of the integration of the created IP with the Zynq device. It will also discuss the creation of some basic device drivers, showing how software can be written to access the registers on the custom peripheral.

Who this course is for:

  • Anyone wish to build expertise in designing Custom AXI interface for Zynq Devices
  • Developing Hardware Accelerators with Verilog RTL

Instructor

Kumar Khandagle
FPGA Developer Lead @ FinTech
Kumar Khandagle
  • 4.5 Instructor Rating
  • 1,425 Reviews
  • 6,154 Students
  • 20 Courses

I am working as FPGA Developer Lead in India's Finest Financial Technology Firm for the development of a next-generation High-Frequency Trading platform on Xilinx Alveo FPGA Cards. Before Joining Fintech, I spent three years as a VLSI Trainer at Mumbai University, India, and one year as Research Scientist at the Prominent R&D Centre for Applied Electronic Research of India contributing to the development of  Gradient Controller,64 Mhz Receiver on FPGA for Indigenous MRI Machine. During my free time, I love to develop Udemy Courses. I also collaborated with Larsen & Toubro Technology Services, Power International in the development of various FPGA based Systems such as Simultaneous DAQ, Multi-channel Logic Analyzers, and DTS. My area of interest includes Front End VLSI Design, SoC, and Chip Verification.

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