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2021-02-11 19:53:46
30-Day Money-Back Guarantee
IT & Software Hardware FPGA

Building Custom AXI Interface Peripherals for ZYNQ Devices

All about AXI Slave Lite and AXI Stream Interface
Hot & New
Rating: 4.8 out of 54.8 (4 ratings)
39 students
Created by Kumar K.
Last updated 2/2021
English
English [Auto]
30-Day Money-Back Guarantee

What you'll learn

  • Building custom AXI Slave Lite Interface
  • Handling Interrupts with Custom AXI Slave Lite Interface
  • Creating Custom AXI Stream Interface with Vivado Template
  • Building Custom AXI Stream Interface with Verilog RTL
  • Writing Drivers for Custom AXI Interface
  • Interfacing of Custom AXI Interface with Zynq devices

Requirements

  • Fundamentals of Xilinx Drivers and Embedded Design Flow

Description

As system complexities are growing day by day, the Zynq device alone is incapable of providing the same performance and the Pure RTL module or Programmable logic (PL) needs to be integrated along with the Zynq. As Zynq works with Advanced Extensible Peripheral (AXI), it becomes mandatory for FPGA engineers to gain a fundamental understanding of adding AXI Interface to the Verilog RTL. The AXI4 offers different variants to fit diverse application needs. Understanding of the simpler variants such as AXI Lite and AXI Stream Interface lays a foundation for building an understanding of the complex AXI4 variant such as AXI Full.   

This course focuses on the usage of the Vivado IP Integrator and Vivado RTL integration for building the custom AXI interface for pure Verilog modules. There are four ways to achieve the addition of the AXI interface to the Verilog RTL viz. Using Vivado IP Packager, Vivado RTL Integration, Using System Generator, Using Vivado HLS. The course discusses two methodologies viz. Vivado IP Packager and Vivado RTL Integration in details with a simple example along with the demonstration of the integration of the created IP with the Zynq device. It will also discuss the creation of some basic device drivers, showing how software can be written to access the registers on the custom peripheral.

Who this course is for:

  • Anyone wish to build expertise in designing Custom AXI interface for Zynq Devices
  • Developing Hardware Accelerators with Verilog RTL

Course content

11 sections • 43 lectures • 4h 52m total length

  • GIT Repo for the Course
    00:00

  • Preview15:07
  • Building AXI Lite Interface without I/O Port P2
    14:24

  • Building AXI Lite Interface with only Output Port P1
    13:32
  • Building AXI Lite Interface with only Output Port P2
    07:43
  • Building AXI Lite Interface with Input and Output Ports P1
    10:05
  • Building AXI Lite Interface with Input and Output Ports P2
    03:47
  • Code and BD
    00:29

  • AXI Slave lite Interface with existing Verilog RTL P1
    13:05
  • AXI Slave lite Interface with existing Verilog RTL P2
    05:23

  • Interrupt with Verilog RTL P1
    06:00
  • Interrupt with Verilog RTL P2
    13:02
  • Code
    00:25

  • Interrupt with Vivado Template P1
    14:23
  • Interrupt with Vivado Template P2
    03:06
  • Interrupt with Vivado Template P3
    20:39
  • Modified Vivado Template Code
    08:38
  • Modified C driver
    00:11
  • Modified H driver
    01:13
  • SDK Code
    00:13

  • Preview05:17
  • Preview02:19
  • Building AXIS Interface with Vivado Template P2
    01:26
  • Building AXIS Interface with Vivado Template P3
    04:54
  • Building AXIS Interface with Vivado Template P4
    07:39
  • Building AXIS Interface with Vivado Template P5
    03:31
  • Building AXIS Interface with Vivado Template P6
    09:45
  • Building AXIS Interface with Vivado Template P7
    11:07
  • Adding ILA Probe to the Interface
    04:58
  • Building Complex FSM with existing FSM for AXIS
    09:45
  • Code and BD
    00:59

  • Building AXIS Master and Slave Interface with Vivado Template P1
    16:00
  • Building AXIS Master and Slave Interface with Vivado Template P2
    04:28

  • Preview10:50
  • Building AXIS Slave Interface with Verilog P2
    12:26
  • Building AXIS Slave Interface with Verilog P3
    04:13
  • Code and BD
    00:35

  • Building AXIS Master Slave Interface with Verilog P1
    16:32
  • Building AXIS Master Slave Interface with Verilog P2
    06:43
  • Code and BD
    00:25
  • Code and BD
    00:38

Instructor

Kumar K.
FPGA Developer Lead at FinTech
Kumar K.
  • 4.4 Instructor Rating
  • 229 Reviews
  • 1,270 Students
  • 10 Courses

I am working as FPGA Developer Lead in India's Finest Financial Technology Firm for the development of a next-generation High-Frequency Trading platform on Xilinx Alveo FPGA Cards. Before Joining Fintech, I spent three years as a VLSI Trainer at Mumbai University, India, and one year as Research Scientist at the Prominent R&D Centre for Applied Electronic Research of India contributing to the development of  Gradient Controller,64 Mhz Receiver on FPGA for Indigenous MRI Machine. During my free time, I love to develop Udemy Courses. I also collaborated with Larsen & Toubro Technology Services, Power International in the development of various FPGA based Systems such as Simultaneous DAQ, Multi-channel Logic Analyzers, and DTS. My area of interest includes Front End VLSI Design, SoC, and Chip Verification.

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