Building Custom AXI Interface Peripherals for ZYNQ Devices

Name: Building Custom AXI Interface Peripherals for ZYNQ Devices
Rating: 4.2 (71 reviews)

All about AXI Slave Lite and AXI Stream Interface

Created byKumar Khandagle

Last updated 11/2021

English

English [Auto],

What you'll learn

Building custom AXI Slave Lite Interface
Handling Interrupts with Custom AXI Slave Lite Interface
Creating Custom AXI Stream Interface with Vivado Template
Building Custom AXI Stream Interface with Verilog RTL
Writing Drivers for Custom AXI Interface
Interfacing of Custom AXI Interface with Zynq devices

Course content

13 sections • 69 lectures • 7h 3m total length

Interface Type1:35
Design a custom IP using light and streaming AXI interfaces for Zynq devices, choosing slave or master configurations and a vado template or verilog RTL, totaling 12 combinations.
Course Framework6:50
Learn a framework for building AXI interface peripherals on Zynq devices, from slingblade and Vivado templates to iReport, interrupts, and DMA-enabled master and stream interfaces.

Agenda0:29
Learn how to add an axi interface peripheral to an ip on Zynq devices, using the provided template and focusing on interface integration.
Slave Lite Interface without I/O Ports P1 : Creating IP8:17
Create a slave lite ip for an axi interface on zynq devices without external i/o, implementing a 32-bit addition with input and result registers and generating write and read logic.
Slave Lite Interface without I/O Ports P2 : Creating IP6:54
Design and implement a slave lite interface without I/O ports by creating an IP, using non-blocking assignments, registers, and clock-driven data expansion and read/write logic.
Slave Lite Interface without I/O Ports P3 : Creating IP4:44
Create a custom IP for a slave lite interface on a zynq device, package and merge changes, validate the design, and automatically add the IP to the catalog.
Slave Lite Interface without I/O Ports P4 : Creating C Application10:08
Develop a C application to configure and verify a slave lite interface peripheral on Zynq devices, including project setup, IP verification, and address-based read and write operations.
Slave Lite Interface without I/O Ports P5 : Creating C Application3:58
use the alternate method with the library to read and write 32-bit values from a specified base address plus an offset, verify with distinct input data, and print the results.
C Code0:16

Agenda0:40
Explore adding input and output ports to our ip, enabling an external stimulus to control and operate the axi interface peripherals on Zynq devices.
Adding Output port to Slave Lite Interface P16:51
Add a four-bit output port to a slave lite interface P1 in a Zynq axi design, package the IP via the IP packager, and verify connections in the block design.
Adding Output port to Slave Lite Interface P24:00
Learn how to integrate a custom AXI slave lite interface with a Zynq processing system by adding an output port, mapping constraints, performing synthesis, and generating the bitstream.
Adding Output port to Slave Lite Interface P33:53
Add an output port to the slave lite interface p3 by writing to the base address and observing the changes after building the bitstream and programming the fpga.
Adding Input and Output ports to Slave Lite Interface P16:19
Add input and output ports to the slave lite interface p1, wiring push buttons and switches for real-time display, then modify and package the IP.
Adding Input and Output ports to Slave Lite Interface P25:07
Add input and output ports to the slave lite interface P2, including clock and reset, and prepare HDL wrapper and pin constraints for synthesis and bitstream on a Zynq device.
Adding Input and Output ports to Slave Lite Interface P32:38
Create a new application project, add input and output ports to the slave lite interface p3, and drive a push button to control LEDs while validating the 0101 register pattern.

Agenda0:44
Explore the signals that enable read and write transactions in a streamlined AXI interface, detailing how input and output communicate different states and support real-time data flow.
Understanding Mandatory Signal: Master Write to Slave (Writing Ops) P17:29
Master writes to a slave in a custom axi peripheral, detailing five channels for address/control, write data, and write response, and covering read operations and signaling.
Understanding Mandatory Signal: Master Write to Slave (Writing Ops) P25:41
Explain the mandatory master-to-slave write operation, detailing the write address, write data, and write response channels and their valid and ready handshakes, including how a zero response signals success.
Understanding Mandatory Signal: Master read from Slave (Reading Ops)3:02
Explain how a master initiates a read from a slave by sending address and control information, then receives data when the slave is ready for a successful transaction.
Other Signals in Slave Lite Interface10:13
Explore the slave lite interface signals for Zynq devices, detailing clock and reset, aw and w data channels, valid/ready handshakes, address and access permissions, and b responses.
Block Design used in Demonstration4:17
Begin with a template and add islet groups to analyze signals in an AXI-based Zynq design. Configure the Zynq processing system and connect blocks to enable hardware transactions.
Analyzing Signals on ILA Probe13:16
Analyze write and read transactions on the ILA probe to observe address sequencing, wvalid, aw, wdata, wstrb, and ready and response signals in incremental burst mode.

Agenda1:23
Focus on three aspects of AXI-based peripheral interfaces on Zynq devices: integrating an existing idea into a template, controlling the flow, and applying a real scenario to deepen understanding.
Add Existing RTL : Delay Generator P113:18
Develop a 32-bit delay generator IP for a Zynq device, implementing start, reset, and done signals, and packaging the design through synthesis and block design.
Add Existing RTL : Delay Generator P25:21
Develop and test a delay generator IP for a zynq AXI peripheral by exporting the IP, configuring a user-specified delay, and validating completion conditions through debugging runs.
Adding Existing RTL : Multiplier P110:54
Add an existing rtl multiplier to the Zynq axi peripheral template, configure a 16-bit bus, and map ports for a clocked design. Validate with behavior simulation; package an external wrapper.
Adding Existing RTL : Multiplier P24:41
Add an existing rtl multiplier (p2) to a new application project, configure addresses and data registers, and validate the multiplication interface through test inputs and outputs.
Adding Exisitng RTL : COMPLEX FSM P18:32
Learn how to integrate an existing RTL complex FSM to control a serial data transfer, detailing start, stack, 32-bit data, control signals, and the complete send-done flow.

Agenda0:46
Outline agenda for building axi interface peripherals on Zynq devices, focusing on a non-interrupt driven approach to understand driver, sensing signals in processing system, and a template for an engine.
Fundamentals of Interrupt C Application12:31
Initialize the periphery and interrupt infrastructure, configure and enable the exception handler, and implement an interrupt service routine to manage switch state changes via GPIO events, in an interrupt-driven workflow.
Adding Interrupt with RTL P111:36
Design and verify a simple RTL interrupt module for a Zynq AXI peripheral, using a clock, start signal, and a 32-bit delay counter to trigger an interrupt.
Adding Interrupt with RTL P215:02
Develop and integrate an interrupt driven RTL peripheral for Zynq devices by initializing config structures, registering exception and interrupt handlers, enabling and prioritizing the interrupt, and validating with FPGA programming.
Code0:27

Agenda0:51
Explore how to integrate the existing block design into the provided template for an axi interface, including adding an intro and modifying the template, as outlined in the agenda.
Using Vivado Interrupt Template Code P114:45
Use the Vivado interrupt template to create and enable an axi-based peripheral for a Zynq device, integrate it in a block design, and manage global interrupt enable and acknowledge signals.
Using Vivado Interrupt Template Code P224:15
Learn to export a bitstream, launch the sdk, and implement a Vivado interrupt template code p2 for a Zynq axi peripheral, covering initialization, exception handling, and global interrupt enable.
Code0:30
Modifying Delay of the Vivado Interrupt Template6:47
Modify the Vivado interrupt template to create a five-second delay by configuring a 50 megahertz clock, adjusting a 32-bit counter, and updating the IP, repackage, and program the FPGA.
Generating Continuous Interrupt P14:48
Generate a continuous interrupt on a Zynq AXI peripheral by configuring a reset-driven counter to create a five-second delay, modifying the IP in Vivado, and updating the IP package.
Generating Continuous Interrupt P22:14
Create a new application project after hardware spec changes, export the bitstream, program the device, and configure code to generate continuous interrupts every five seconds.
Blinking Effect with Interrupt16:38
Learn to generate a blinking effect on a Zynq device by wiring an AXI IP, configuring GPI and GPO, and handling interrupts to drive the blink rate.
Code0:40

Agenda0:39
Outline the section agenda, highlighting three domains used for transfer and how to apply a viral template to an ip.
Creating Master Interface with Vivado Template P118:23
Develop a master AXI interface using a vivado template p1 and integrate a slave interface to control AXI transactions, package the IP, and generate the bitstream for a zynq device.
Creating Master Interface with Vivado Template P26:54
Learners build and test a master AXI interface with the Vivado template P2, starting and monitoring transactions, writing 16 samples, and reading back 32-bit data to verify memory access.
Code0:12

Agenda0:48
Explore adding a live stream interface to an IP and handling transactions via memory-map to stream conversion. Compare streaming interfaces with a full DMA to prepare for the next section.
Building AXIS Slave Interface P120:38
Learn to build an axis slave interface for Zynq devices using the Vivado template, creating a streaming data path, implementing a simple state machine, and integrating into a block design.
Building AXIS Slave Interface P26:36
Follow step-by-step synthesis design setup to configure connections and generate a bitstream, then export and program a fpga, and run a hello world application to test the axis slave interface.
Code0:13
Building Complex FSM with existing FSM for AXIS9:45
Extend an existing FSM to build a complex AXIS-based application by adding an IP package, defining states and counters, then repackage and program the bitstream to the hardware.
Code1:01

Agenda0:39
Explore how to enable bidirectional communication between memory-mapped and streaming interfaces in AXI peripherals for Zynq devices, and demonstrate a complete hardware design approach.
Creating AXIS Master Interface P119:32
Create and package an AXIS master interface P1 as part of an IP, configuring a sleep streaming interface. Connect a master to a slave axis to enable streaming data processing.
Creating AXIS Master Interface P24:06
Learn to implement an AXIS master interface by configuring DHS addresses, performing IXI DMA transfers for read/write, and validating results by squaring and printing the received value.
Code0:19

Requirements

Fundamentals of Xilinx Drivers and Embedded Design Flow

Description

As system complexities are growing day by day, the Zynq device alone is incapable of providing the same performance and the Pure RTL module or Programmable logic (PL) needs to be integrated along with the Zynq. As Zynq works with Advanced Extensible Peripheral (AXI), it becomes mandatory for FPGA engineers to gain a fundamental understanding of adding AXI Interface to the Verilog RTL. The AXI4 offers different variants to fit diverse application needs. Understanding of the simpler variants such as AXI Lite and AXI Stream Interface lays a foundation for building an understanding of the complex AXI4 variant such as AXI Full.

This course focuses on the usage of the Vivado IP Integrator and Vivado RTL integration for building the custom AXI interface for pure Verilog modules. There are four ways to achieve the addition of the AXI interface to the Verilog RTL viz. Using Vivado IP Packager, Vivado RTL Integration, Using System Generator, Using Vivado HLS. The course discusses two methodologies viz. Vivado IP Packager and Vivado RTL Integration in details with a simple example along with the demonstration of the integration of the created IP with the Zynq device. It will also discuss the creation of some basic device drivers, showing how software can be written to access the registers on the custom peripheral.

Who this course is for:

Anyone wish to build expertise in designing Custom AXI interface for Zynq Devices
Developing Hardware Accelerators with Verilog RTL

Building Custom AXI Interface Peripherals for ZYNQ Devices

What you'll learn

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Course content

Section 0 : Course Framework2 lectures • 8min

Building AXI Slave Lite Interface : Using Vivado Template without I/O ports7 lectures • 35min

Building AXI Slave Lite Interface : Using Vivado Template with I/O ports7 lectures • 29min

Understanding AXI4-Lite Signals7 lectures • 45min

Adding AXI Lite Interface for existing Verilog Code6 lectures • 44min

Adding Interrupts to Slave Lite Interfaces5 lectures • 40min

Adding Interrupts with Vivado Template9 lectures • 1hr 11min

Adding Master Interface4 lectures • 26min

AXI Stream Slave Interface with Vivado Template6 lectures • 39min

AXI Stream Master Interface with Vivado Template4 lectures • 25min

Requirements

Description

Who this course is for: