Crash Course Digital Electronics

Explore how binary bits drive digital logic by using transistors to implement not, and, or gates, the foundation of modern computing from vacuum tubes to silicon.

Explore how transistors act as switches to implement binary logic and build the three basic gates: not, and, or, underpinned by Boolean algebra and voltage-level inputs.

Learn how not, and, or gates form the basis for building xor from transistors, and why engineers move from transistors to logic gates to design processors.

Explore how computers store numbers using binary representations, from bits and bytes to 32- and 64-bit systems, including sign bits, memory addresses, and common data units.

Learn how floating-point numbers are stored in IEEE 754 32-bit single precision, with sign, exponent, and significand. Discover how ASCII and Unicode encode letters and symbols for text across languages.

Explore the arithmetic logic unit (ALU), the computer's math brain, focusing on addition and basic operations built from AND, OR, NOT, and XOR gates, including the Intel 74181.

Design a half-adder with inputs A and B, producing sum via XOR and carry via AND, enabling a one-bit addition.

Explore the full-adder, which takes A, B, and C to produce sum and carry. Build it from two half-adders and an OR gate, then apply to multi-column addition.

Explore how an 8-bit ripple carry adder adds two numbers using half-adders and full adders, highlighting overflow, carry propagation, and the move to carry-lookahead adders for speed.

Explore the logic unit of the ALU, performing and, or, not operations and a zero test with or and a not gate, noting 4-bit and 8-bit ALU flags.

Explore how random access memory stores data while powered, and compare RAM with persistent memory. Build a one-bit storage circuit and begin forming a memory module for future CPU integration.

Create a memory element by looping back an or gate and an and gate, forming an and-or latch with set and reset inputs to write and read a single bit.

Open the gated latch by turning on the write enable to store a data bit and lock it when the enable goes low.

Learn how registers store multi-bit data using latch matrices, with one data wire and shared write enable and read enable, row-column addressing, and multiplexers.

Explore how a 256-bit memory becomes a byte-addressable SRAM with two 4-input decoders for rows and columns, enabling random access memory (RAM) with read/write control.

We introduce the central processing unit, show how it executes instructions via the alu and registers, and explain the 16-location 8-bit ram with opcodes and the instruction and address registers.

Explore the fetch-decode-execute cycle by fetching an instruction from RAM, decoding the load_a opcode, and loading the RAM value into register A via control logic.

Execute the fetch–decode–execute cycle to run the program, with the control unit configuring RAM, registers A and B, and the ALU to perform add and store operations.

Explore how a clock drives the cpu through fetch-decode-execute, measure clock speed in hertz, and compare generations, with overclocking, underclocking, and dynamic frequency scaling.

Explore how a programmable CPU uses an ALU with a four-instruction program—LOAD_A, LOAD_B, ADD, and STORE_A—to process memory data via 4-bit opcodes and registers A and B.

Add subtract and jump instructions, including jump negative and halt, to control flow and separate code from data in memory, using the ALU negative flag.

Discover how conditional jumps prevent overflow and control loops in an 8-bit processor, compute remainders, and how software enables division beyond the arithmetic logic unit.

Discover how high clock speeds and expanding instruction sets create RAM bottlenecks, and how a cache on the CPU reduces data transfer delays to boost performance.

Accelerate CPU performance by loading data blocks from RAM into an on-chip cache, boosting cache hits, using the cache as scratch space, and managing dirty bits with write-back and synchronization.

Parallelize the processor workflow by overlapping fetch, decode, and execute stages to increase throughput, turning one instruction per clock cycle and tripling CPU efficiency.

Explore how a pipeline runs an instruction each clock cycle to boost throughput while managing hazards from data dependencies through look ahead, stalls, and out-of-order execution.

conditional jump instructions affect execution flow, causing stalls; speculative execution and branch prediction help keep pipes full and improve throughput, with superscalar CPUs delivering multiple instructions per cycle.

Examine superscalar processors that fetch and decode multiple instructions, execute in parallel using duplicate ALUs, and extend to multicore designs for parallel instruction streams.

Explore multi-core and multi-CPU systems, from dual and quad-core chips to Fugaku, a supercomputer with hundreds of thousands of CPUs and millions of cores delivering massive FLOPS.

Trace how programs entered memory through punch cards, from Jacquard's loom to census tabulation, with holes encoding patterns and forming early command sequences.

Examine how early tabulating machines used plug boards to pass signals and how swappable boards enabled different programs, leading to memory-based stored programs and the Von Neumann architecture.

Explore the von Neumann architecture, where data and instructions share RAM, and see how the CPU's ALU, control unit, and registers execute programs via the data and address buses.

Harvard architecture stores instructions separately from data, enabling simultaneous instruction fetch and data transfer via separate buses and memory modules.

Examine how punch card readers load programming data into memory, process stacks of cards, and strip to maintain order, as Sage Air Defense System used 62,500 cards totaling five megabytes.

Panel programming used front-panel switches and indicator lights to enter and monitor memory, as seen with the Altair 8800, highlighting why early programming required hardware knowledge.

Explore how opcodes and memory addresses encode instructions to load data into register A. See an eight-bit instruction where 0010 means load into register A and 1110 designates address 14.

Explore how processors natively speak machine language, the binary instructions they understand. Learn how mnemonics, opcodes, and assemblers translate high-level descriptions into binary machine code.

Explore how assemblers translate human-readable assembly language into native machine code, enabling direct hardware interaction, with labels and jump addresses that simplify programming and manage registers and memory.

Understand how assembly language maps directly to machine instructions and why high-level languages like A-0, designed by Grace Hopper, simplify programming with early compiler translation to machine code.

Explain how high-level programming languages abstract memory and registers through variables, as C demonstrates. Highlight Fortran, released by IBM in 1957, showing shorter programs and faster programmer time despite skepticism.

Explore the evolution of programming languages from COBOL to modern high-level languages, and how compilers enable write once, run anywhere across different machines, lowering barriers to entry.