Computer Organization: CPU Cache and the Memory Hierarchy

Explore the logical model of a cache by visualizing cache lines with valid, tag, and data fields, and how misses load data and use least recently used replacement.

Explore a simple two-line cache in a 16-word memory, using direct addressing, illustrating hits, misses, eviction, and data flow from memory to registers.

Learn how a cache in the memory hierarchy affects average memory access time, using hit ratio and miss ratio to derive the formula C plus (1 minus hit) times M.

Calculate the average CPI for a single-cycle processor with a perfect instruction cache, 90% data-cache hits, 10% misses costing 20 extra cycles; compare with no data cache.

Explore spatial locality as caches exploit neighboring cache blocks, revealing how array access patterns, sequential instruction flow, and object attributes drive efficient memory behavior.

Explain cache blocks in the memory hierarchy, showing how spatial locality reduces misses by loading neighboring data, and how blocks carry multiple words per tag with block offsets.

Determine the cache address partition for a 32-bit word-addressable memory with 64-word blocks, allocating six bits for the block offset and twenty-six bits for the tag.

Explore how write-through caches handle stores, using an lru two-word block, tag and offset, with misses, loads, and writes propagating to main memory.

Explore write allocation in caches, contrasting write allocate and write no allocate policies, and explain how misses trigger memory access or direct writes, with emphasis on write back caches.

Learn how cache associativity shapes hits and misses, comparing fully associative caches, direct map caches, and set associated caches, including two-way set associativity and per-set search behavior.

Store only the tag portion of the memory address in direct mapped caches. Map set index and block offset to unique line and note they do not appear in the cache.

Explore how a direct-mapped cache operates with two lines, explaining block offsets, set indices, and tag fields, including misses, evictions, write back, and a hit example.

Demonstrates a two-set, two-line set-associative cache with a write-back policy, dirty bits, tag fields, and lru replacement, illustrating hits, misses, evictions, and memory writes.

Explore cache eviction algorithms such as LRU, first in, first out, and random eviction, and explain how the optimal policy compares with LRU via past usage and temporal locality.

Examine the cache hierarchy: l1 split into instruction and data caches, then l2 and l3 caches, with access flowing from l1 to l2 to l3 and finally RAM.