Computer Architecture

Show how to build a 4-bit adder with four chained full adders, propagating carries from LSB to MSB. Learn binary addition rules, A and B inputs, and carry outputs.

Create a subtractor using a 2’s complementer in the ALU to compute A minus B as A plus (-B) by inverting bits and adding 1.

Explore how a shifter moves a bit sequence left or right. See how left shifts multiply by two and right shifts divide by two for binary and decimal values.

Explore how binary multiplication works by using an ALU-based multiplier with a product register, multiplicand, and multiplier; shift operations and conditional accumulation realize the final product.

Explore binary division in computer architecture, performing dividend and divisor operations to yield quotient and remainder, using a controller, ALU, shifter, and 2's complement subtraction across 4-bit inputs.

Explore how real numbers are represented in the 32-bit float and 64-bit double formats, detailing sign, exponent with bias, and mantissa, and how converting 23.738 yields 23.738001 due to rounding.

Explore floating-point operations by performing real number addition with exponent alignment, real-number multiplication by mantissa multiplication and exponent addition, and real-number division with mantissa division and exponent subtraction.

The CPU fetches instructions from memory, executes them, and repeats the fetch and execute phases in a continual instruction cycle until the computer powers off.

Explore the instruction set architecture of a 16-bit CPU, including addressing modes, machine and assembly language translation, and the fetch-decode-execute cycle with registers and ALU.

Explore addressing modes in a 16-bit instruction set, including immediate, direct, and indirect modes, their cycle costs, and how the compiler selects the appropriate mode in C/C++.

Differentiate CISC and RISC architectures by instruction length: CISC uses variable-length instructions exemplified by x86, while RISC uses fixed-length instructions exemplified by ARM and MIPS.

Explore external fragmentation in a 64K memory where a 15K program cannot fit contiguously, then learn how 8K pages and the MMU enable paging and better utilization.

Understand how the memory management unit maps a logical address to a physical address via the page table and the TLB, with mode and valid bits.

Data travels from disk to main memory via l2 and l1 caches, transferring in page, block, and word units, with page faults managed by the os to reduce cost.

Describe how a block-based, set-associative cache stores memory data using 8-bit addresses split into tag, set, and word, with lru eviction and write-back versus write-through.

Static RAM powers caches and dynamic RAM forms main memory. Static RAM offers faster access but larger area and higher cost, while dynamic RAM uses capacitors and requires periodic refresh.

Explore three interrupt types in computer architecture: traps as exceptions (divide error, page fault), external hardware interrupts from I/O devices, and internal software interrupts caused by system calls.

Examine IDT and ISR for interrupt handling, with an ISR per interrupt type and the IDT storing ISR entry points in interrupt-number order; Intel uses IDTR, ARM uses address 0.

Explore how a trap triggers an interrupt on divide-by-zero, mapping interrupt 0 with the IDTR to the IDT, and how the divide error handler terminates the process.

Examine how internal interrupts trigger system calls; the CPU loads 0x01 into eax for exit, executes 0x80, and routes to the ISR via the IDTR/IDT to kill Process A.

Explore how external interrupts flow from device controllers through the PIC to the CPU, including IRQ lines, INTR/INTA signaling, and IDT-based ISR handling with a keyboard example.

Compare PIO and DMA for memory-to-I/O data transfers, showing how DMA transfers directly without CPU intervention and frees the CPU for other tasks to boost efficiency.

Explore device configuration of DMA, CPU, and memory, with IO devices like disk and camera connected to device controllers, using DMA request/ack and channels with control, address, and count.

Analyze the DMA write process from disk to memory, detailing preparation, transfer, and completion stages, including a three-byte example, cycle stealing, and the CPU–DMA coordination.

Examine the DMA read process from memory to disk, detailing the preparation, transfer, and completion stages, including DMA controller configuration, cycle stealing mode, and disk interrupt handling.

Explore how hdd data is stored on stacked platters with tracks, cylinders, and sectors using lba addressing, and compare fragmentation effects to ssds, including mbr, fat, and file storage.

Compare hdd and ssd, addressing and access: hdd uses sectors and tracks with chs and sequential access; ssd uses pages and blocks with chs compatibility and random access, avoiding fragmentation.

Compare memory-mapped and isolated I/O methods, explaining shared read/write lines in memory-mapped systems and separate signaling in isolated systems, with example address ranges for memory and I/O spaces.

Explore how analog inputs from cameras and microphones become digital data via ADCs, including sampling, quantization, and encoding, with DMA and PIO for I/O transfer, and DACs for output.

Compare CPU and GPU architectures, noting GPUs have more ALUs and prioritize floating-point performance for multidimensional array calculations, while CUDA enables data flow and parallel computation.