Computer Organization and Architecture - Part 3

Explain how RISC uses a reduced instruction set and load and store. Compare to CISC, with complex instructions and RAM access beyond load and store.

Comparing RISC and CISC shows how basic instructions reduce hardware complexity and power, while compiler efficiency makes high-level code practical, diminishing the need for special instructions.

Explore RISC vs CISC, showing execution time is similar without pipelining, but pipelining makes RISC faster than CISC.

Understand the components of a CPU—the ALU, control unit, and register file—and how they interact with RAM to perform read and write operations.

Compare general-purpose and special-purpose registers, including program counter, instruction register, memory address register, and memory data register, and show how control signals drive CPU operations from RAM to the ALU.

Explains how binary machine instructions use an opcode and operands in a 2-address format with registers, and how addressing modes distinguish between registers, memory addresses, or numbers.

Explore how instructions encode operations with opcode and operands, including how addressing modes—register or direct—determine operand sources and how dedicated versus combined fields represent them.

Explore register addressing mode, where operands reside in central processing unit registers, avoiding memory access for faster operand fetch; the effective address equals the register number.

Register addressing mode shrinks instruction size by using small register numbers, avoiding RAM access for operands; its limited register count and cost limit its universal use.

Explore direct addressing mode, also called absolute or memory direct addressing, where an instruction fetches the operand from a ram address, highlighting slower access and longer instruction length than registers.

Understand how direct and register addressing modes determine the effective address and operand fetch, and how compilers map high-level code to assembly for arrays and pointers.

Explore indirect addressing mode, also called memory indirect or deferred addressing, by showing how two brackets lead to a final operand value via memory addresses, highlighting the effective address.

Explore immediate addressing mode, where the operand is embedded in the instruction, avoiding operand fetch. Limit usage to source operands due to the limited size of the operand field.

Explains immediate addressing mode for constants when converting high level code to assembly, with examples like 5 and 3.14, and contrasts it with direct and register addressing in RISC architecture.

Explore register indirect addressing mode and memory indirect addressing mode. See how pointers and operands move through RAM, and why memory indirect addressing is used for pointers.

Explore how register indirect addressing mode enables linear, contiguous access to array elements in memory, with auto increment and auto decrement variants, and how assembly loops model high-level iteration.

Explore auto increment addressing mode, a variant of register indirect addressing, enabling linear array access by auto incrementing the address register after each load and enabling single-instruction looping.

Explore auto decrement addressing mode and its auto increment counterpart, including pre and post variants, with examples of stack and array access using R1 and M[R1].

Examine three displacement addressing modes—index, base, and PC relative—and how each computes an operand's effective address by combining a number with a register, as in 1000(R2) or R2(1000).

Explore indexed addressing mode, where the index register and base address access array elements, enabling both linear and random access in assembly code.

Explore base addressing mode (also called base register or base relative addressing), where a base register plus an offset yields the effective address for branching.

Base register addressing mode uses a base register plus displacement to form the effective address, enabling program relocation for control instructions. It avoids the relocation issues of direct addressing.

Differentiate base addressing mode and indexed addressing mode by highlighting base and index registers, their use for program control and data transfer, and how addressing enables relocation and array access.

Pc relative addressing mode uses program counter as the base for branch and jump instructions, adding the offset to next instruction's address, unlike base addressing mode using a base register.

Explore implied addressing mode, where operands are not explicit; learn default accumulator usage, effects on instruction length and bus, and direct vs two- and three-address formats, with CPU organization notes.

Examine CPU organization, including the ALU and control unit, and compare general register, single accumulator, and stack-based architectures, highlighting control signals and hardware circuits.

Explore the general register CPU organization, where the ALU connects bidirectionally to all general-purpose registers (R0–R63) to perform ALU operations via load and store instructions.

Explain single-accumulator CPU organization by replacing many general-purpose registers with a single accumulator connected to the ALU, highlighting lower cost but reduced efficiency due to frequent RAM access.

Explore stack based cpu organization, where a stack implemented inside registers uses the top of the stack with the accumulator and memory data and address registers to perform ALU operations.

This lecture explains load and store in a stack based cpu, including push and pop operations and how the ALU uses the top of the stack.

Explore stack-based CPU organization, showing how push and load place operands on the stack, how top of stack and accumulator interact during addition, and why operand order matters.

Compare memory stack and register stack cpu organization, noting that main memory access for operations is costly and that register-based organization offers a simpler, faster design.