Computer Architecture and Computer Organization Masterclass

Why should you consider enrolling on this Computer Architecture & Computer Organization Masterclass?

• The course instructor is a lecturer teaching Computer Organization and Computer Architecture subjects for 3+ years.

• This course is designed in 2022 with the latest Computer Organization and Computer Architecture lessons, examples and activities.

• This course covers everything you need to master the subject without enrolling with other parts/courses related to the topic.

• This course includes lecture notes/slides as downloadable materials.

• You will be part of the 4000+ student community already in one of my courses.

I invite you to check the free provided videos and course outline. Then, if you are happy, enrol with this latest and best Computer Organization and Architecture course.

All-in-one Complete Computer Organization and Architecture Course  Outline

Chapter 01: Introduction

1.1 Introduction to Computer Organization and Architecture

1.2 Computer Level Hierarchy

Chapter 02: Fetch - Decode - Execute Cycle

2.1 Fetch Decode Execute Cycle Explained Part 1

2.2 Fetch Decode Execute Cycle Explained Part 2

Chapter 03: Assembly Language Programming with the Little Man Computer

3.1 What is the Little Man Computer

3.2 Programming the Little Man Computer

3.3 Fetch Decode Execute Cycle Explained using the Little Man Computer

3.4 Writing Assembly Language Code

Chapter 04: Instruction Set Architecture (ISA)

4.1 Introduction to ISA

4.2 CISC and RISC

4.3 Instructions

4.4 Number of Addressing

4.5 Addressing Modes

Chapter 05: CPU Benchmarking

5.1 Introduction to CPU Benchmarking

5.2 Calculating CPU Time

5.3 Understanding CPU Clock

5.4 Calculating CPU Time

5.5 Exercise - Solving CPU Time Calculations

5.6 Exercise - Solving CPI Calculations

Chapter 06: CPU Organization and Structure

6.1 Introduction to CPU Structure

6.2 Registers in CPU

6.3 Understanding CPU Interruptions

6.4 Techniques to Improve CPU Performance

Chapter 07: CPU Pipelining

7.1 What is CPU Pipelining

7.2 Resource Hazards

7.3 Data Hazards

7.4 Control Hazards and Branch Prediction

7.5 Branch Prediction Strategies

7.6 Practical Example for Pipelining - Intel 80486

7.7 CPU Overclocking

Chapter 08: Input-Output Organization

8.1 Introduction to I/O

8.2 I/O Mapping

8.3 Asynchronous Data Transfer

8.4 Modes of Data Transfer

Chapter 09: Memory Organization

9.1 Introduction to Memory Hierarchy

9.2 Deep dive into Computer Memory Hierarchy

9.3 The Principal of Locality

9.4 Memory HIT rate and MISS rate

9.5 Cache Performance and Optimization

9.6 Exercise - Calculating Miss Rate

9.7 Memory Technology

9.8 DRAM Technology

9.9 How a DRAM Works

9.10 DRAM Read Cycle Deeply Explained Step by Step

9.11 SDRAM and DDR SDRAM Explained

Chapter 10: Hierarchical Bus Organization

10.1 Introduction to Hierarchical Bus Structures

10.2 Single and Multiple Bus Implementations and Examples

10.3 Bus Types, Timing, and Additional Details

Chapter 11: Conclusion

11.1 Summary