Computer Architecture & Organization Part 1 : Cache Memory

Learn how direct mapping in cache memory uses paging concepts to convert logical addresses to physical addresses via page tables, frames, and cache lines, mapping frames to lines with tags.

Explore direct mapping with a practical example, showing how a logical address becomes a physical address via page tables, frames, and how the cache uses tag and line number.

Learn direct mapping using a 32-frame RAM and a 4-line cache, mapping frames to cache lines via modulo, with binary line numbers, tags, and offsets.

Explore direct-mapped cache operation by identifying which RAM frames occupy the four cache lines, using a 4-bit tag and 2-bit line number, and determining cached bytes.

Compute tag bits and tag directory size for a 256 kb main memory with 16 cache lines and 2^10-byte blocks; conclude 4 tag bits and an 8-byte tag directory.

Analyze a byte-addressable cache memory with 256 kb size, 1 kb blocks, and 8-bit tags. Determine the RAM size as 64 MB and the tag directory size as 256 bytes.

Derive the cache organization for 32 gb ram with 35-bit address, using 2^13-byte frames and 10-bit tags to yield 2^12 lines, a 2^25-byte cache, and a tag directory.

Understand how direct mapping uses a single comparator to determine cache hits by matching tag bits with the line tag, and how comparator size depends on tag width.

Direct mapping routes each frame to a single cache line, causing capacity and conflict misses; capacity misses stem from limited space, while conflict misses stem from fixed mappings.

Explain the locality of reference, contrasting spatial locality and temporal locality, and show how cache memory uses page-level transfers from RAM to exploit these patterns.

Explore how associative mapping lets any RAM frame go to any cache line, eliminating conflict misses but increasing hardware cost due to tag comparators.

Examine direct and associative mapping in cache memory, detailing tag-based comparisons across lines, frame placement, and how CPU addresses translate from logical to physical addresses via frame number and offset.

Examine an associative cache memory with four lines and four-byte frames, using tag and offset to locate frames (13, 23, 3, 11) and determine the corresponding byte ranges.

Explore associative cache mapping with a 512kb RAM and 256 byte blocks in a byte-addressable system, deriving tag size, frames, and 128 comparators.

Solve a 256 kb cache with 2 kb blocks using associative mapping, deriving a 28-bit address, 128 lines, a 2176-bit tag directory, and 256 mb ram.

Compute the tag size for an 8 gb RAM with 8 kb blocks in an associative cache by breaking a 33-bit address into a 13-bit offset and 20-bit tag.

Explore set associative mapping that blends direct and associative techniques to achieve medium misses and balanced tradeoffs, using sets and tags to map RAM to cache.

Explore how direct, fully associative, and set-associative cache mappings determine comparator counts and conflict misses, with examples of line sets, frames, and replacement impacts.

Analyze a 33-bit physical address in a 2-way set-associative cache to determine 2^12 sets, 2 lines per set, 2^13 total lines, and 2^24 bytes of cache.

Compute cache configuration from eight kilobytes and 128-byte lines in a four-way set-associative mapping, determining the number of lines, sets, frames, tag bits, and comparators.

Analyze an 8-way set-associative cache with 256 lines and 32 sets. The system uses 22-bit addresses split into 5-bit set, 7-bit tag, and 10-bit offset, with eight tag comparisons.

Solve a 4-way set-associative cache problem by computing cache size from tag, set, and offset fields within a 27-bit physical address, showing a total size of 512 kb.

Solve problem 5 by analyzing a one megabyte, eight-way set-associative cache with an 11-bit tag. Conclude the main memory size is 2^28 bytes (256 megabytes).

Map a memory block to a cache set using j mod v in a k-way set-associative cache, then select a line from the set's first to last line.

In a direct-mapped 32 kb cache with 32-byte blocks and 32-bit addresses, the cache indexing uses 10 bits (line number) and the tag uses 17 bits.

From a 40-bit physical address in an eight-way set-associative 512 kb cache, the set number and offset together use 16 bits, leaving a 24-bit tag.

Analyze a 256 kilobyte cache, four-way set-associative, with 32-byte blocks and 32-bit addresses; compute tag directory size as 18 bits per line across 8192 lines, about 18 kilobytes.

Demonstrate set-associative cache mapping: a main memory block k maps to cache set k mod c, using the remainder to identify the target set in a two-block-per-set cache.

Understand how a word differs from a byte in a byte addressable RAM, and how frame number and frame offset define physical addresses accessed via MAR, MDR, and buses.

This lecture explains word-addressable memory where one word equals two bytes, addresses refer to words, not bytes, and the physical address is 31 bits comprised of frame and word offset.

Analyze a word-addressable, 32-bit memory system with 2^36 bytes memory and 2^12-byte frames, yielding a 34-bit physical address, 24-bit frame number, and 10-bit offset.

Explain how a byte-addressable system with 1 word = 4 bytes uses a 32-bit physical address, frames, and word-offsets to fetch a byte by retrieving a full word.

solve a 4k word cache problem with 64-word lines in a 4-way set-associative mapping, and find 4 bits for the set number and 6 for the word number.

Compute tag, set, and word field sizes for a 4-way set associative cache with 128 lines, 64-word lines, and a 20-bit address.

Explore a 4-way set-associative cache of 16 kb with 8-word lines and 4 gb ram, and determine 20-bit tag, set, and offset sizes.

Explain a 4-way set-associative cache with 128 lines and 16,384 memory blocks, and derive 22-bit address fields: tag 9, set 5, and word 8.

Explain how multiple words per cache block exploit spatial locality, differentiate it from temporal locality, and discuss miss penalty when fetching pages from RAM to cache.