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VERILOG / VHDL guided project tutorial UART design on FPGA
Rating: 4.1 out of 5(21 ratings)
84 students

VERILOG / VHDL guided project tutorial UART design on FPGA

Design of UART on FPGA using VHDL / verilog programming (Guided project)
Created byEzeuko Emmanuel
Last updated 10/2023
English
English [Auto],

What you'll learn

  • the student will learn how to design a half-duplex and also a full duplex transceiver.
  • the student will learn about baud rates, how to design one and the different lists of standard baud rates
  • the student will learn how to design a UART serial communication protocol and implement it on an FPGA Board
  • design UART transmitter AND receiver on FPGA with vhdl code, and simulate on logism
  • the student will learn how to convert serial bits to parallel bits and vice versa, and also implement in VHDL
  • the student will also learn some commonly used VHDL structural blocks like shift registers, parallelizer, serializer,
  • design UART transceiver on FPGA with vhdl code, and simulate on logism

Course content

5 sections • 20 lectures • 3h 37m total length

  • 01- Introduction0:36

    Design and simulate a full duplex and half duplex UART serial protocol on an FPGA, using Verilog/VHDL with hands-on coding and Logisim-based circuit visualization.

  • Download zipped project folder0:01
  • 02 - How to ask the instructor questions0:58

    Click on Q&A, type your question, publish it, and receive answers from the instructor who actively checks and responds.

  • 03 - UART configuration13:10

    Master uart theory and its asynchronous serial transmission, including baud rate, start/stop bits, parity, and rts/cts, and learn clocking via board clock and oversampling.

  • 04 - introducing the logism design18:05

    Explore a verilog/vhdl guided UART design on FPGA, demonstrated in logisim, featuring two UART transceivers with shared lines, baud clock generation, and full-duplex operation.

Requirements

  • No external hardware needed. We would simulate the FPGA design in logism. Basic knowlegde of vhdl and how to use logism may be required.

Description

This is a practical course, that will teach you how to design your first UART project on FPGA  using Verilog HDL programming language.

In this course, you will learn the difference between a full duplex UART transmission and a half-duplex transmission including their technical difference.  You will how to use LOGISM EDA tool to design, test and simulate logic circuits.

You will a baud clock, learn how it is synthesized from system clock and how to calculate the frequency of generation.

you will learn what a baud rate means and also learn the standard baud rates and how to generate them from the system clock.

You will learn how to design and wire the receiver and transmitter to their baud clocks and how they are joined together to make up the transceiver.

The course is divided into three sections: the receiver, the baud generator and transmitter.

This a 17 video course. each module teaching about a particular part of the design.

a lot of visuals, arrows, pictures were used to make the tutorials easy to understand.

kindly use the logism circuit file while watching the tutorial for easy understanding.


You will get the VHDL scripts and the logism circuit attached to lesson two.

No hardware is required just your pc.

It was kept brief and straight to the point.

Who this course is for:

  • Students with basic knowledge of VHDL, looking for a project to design

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