Verification Series Part 1: SystemVerilog Essentials

Generate global, control, and data signals in SystemVerilog testbenches, and learn to produce clock signals without randomization. Master using initial and always blocks to implement variable-rate and fixed clocks.

Identify signals in test benches as global, data, and control categories, including clock, reset, write data, and address. Learn to generate random stimuli with an initial block for verification.

Explore how to use initial blocks in SystemVerilog testbenches to initialize global signals like clock and reset, enable waveform viewing with dumpfile and dumpvars, and generate startup stimuli.

Explore how the initial block in a SystemVerilog testbench starts at time zero, supports single or multiple statements, and how reg holds its value to the end of simulation.

Execute code to observe waveform and console outputs in a Verilog simulation; clock stays zero, reset lasts 30 ns, temp is random, monitor prints 0 ps, 10 ns, 20 ns.

Explains the always block in SystemVerilog, including always_comb, always_ff, and always_latch, and contrasts sensitivity lists in design versus testbenches, plus generating clocks, data, and resets for stimulus.

Learn to use an always block in SystemVerilog test benches to generate clocks (100, 50, 25 MHz) by toggling with the complement operator, while ensuring proper initialization and finish.

Align the first edges of clock_100, clock_50, and clock_25 with the reference clock by delaying signals to achieve zero phase difference and synchronized periods.

Explore the timescale directive in SystemVerilog, defining time unit and precision, and how it governs floating point representations, rounding, and decimal digit limits across nanosecond and picosecond scales.

Demonstrates generating 16 mhz and 8 mhz clocks with delays, initialization, and timescale concepts, and shows how time precision governs fractional delays and accurate period results.

Generate a reconfigurable clock waveform from user inputs, compute period, on-time, and off-time from frequency and duty cycle, while applying phase offset and a nanosecond timescale.

Demonstrates generating a clock signal using phase, t_on, and t_off, with an initial block and a clock_generator task to vary phase and observe the waveform.

Modify the code to accept frequency, duty cycle, and phase difference and compute period, T_on, and T_off for a configurable clock; implement calculate to output phase_out, T_on, and T_off.

Explore SystemVerilog test benches by initializing global signals, applying a 30 ns reset, generating a clock with an always block, and ending simulations after waveform capture.

Explore SystemVerilog fundamentals by distinguishing two-state and four-state data types, and mastering array varieties: fixed, dynamic, and queues, along with real examples of initialization, looping, and queue read/write techniques.

explore the three datatype categories in systemverilog, learn when to use reg (rectangle) for registers and wire for nets, and apply the correct type for procedural versus continuous assignments.

Explore SystemVerilog datatypes, from real floating-point to two-state and four-state fixed types, with 8-, 16-, 32-, and 64-bit signed and unsigned ranges.

Explore how SystemVerilog maps variable types to hardware with wire and reg ports and posedge clocked blocks, and learn to match bit widths for compatible ports.

Explore Verilog data types for hardware, variables, and simulation, including reg and wire, signed and unsigned forms, time and real data types, and port size compatibility for timing samples.

Learn SystemVerilog datatypes, including two-state and four-state, with bit and unsigned/signed types, initialization rules, and sizing using 8'd, 8'h, or 8'b formats.

Demonstrates systemverilog data types by using byte and shortint, showing 8-bit signed ranges and unsigned 0 to 255, with display to observe overflow.

Demonstrates using time and real_time data types to store fixed-point and floating-point simulation times, samples current time with dollar_time and dollar_real_time, and explains timescale and precision effects.

Demonstrate a simple 2:1 mux using reg in a combinational always block. Compare reg versus wire and logic types while wiring y via a temporary variable.

Explore how wire, reg, and logic types affect connecting modules in a full adder built from two half adders, including undefined nets and rtl schematics.

Replace wire with logic in a 2:1 mux and confirm rtl analysis with an sv source file. See how logic adapts to reg or wire and bidirectional use in interfaces.

Explore how arrays in SystemVerilog enable collecting multiple transactions from the test generator, monitor, and scoreboard, and compare them against golden data for the DUT.

Declare a fixed-size array in SystemVerilog by starting with a bit data type and eight elements, using the square-bracket size notation. SystemVerilog simplifies size specification compared to Verilog, allows initializing with curly braces to set initial values, and then uses the $size function to verify that array1 is eight and array2 is four.

Learn how to access and print SystemVerilog arrays, including selecting elements by index, updating values (array1[1] = 1), and printing all elements with %p.

Explore how fixed-size arrays behave in SystemVerilog when the size is not specified, including zero size and out-of-bounds updates, and explain two correct methods to initialize or size arrays.

Learn array initialization strategies in SystemVerilog: assign unique values with apostrophe and braces, use repetition operator for duplicates, apply default values, or leave elements uninitialized (two-state zeros, four-state x).

Demonstrates declaring and initializing SystemVerilog arrays, including uninitialized arrays with bit defaults to zero and logic defaulting to x, and integers with unique or repetitive values.

Explore how to use for, repeat, and foreach loops in SystemVerilog to initialize 1D and 2D arrays, update elements, and display results in a testbench.

Explore how foreach loops simplify array iteration in SystemVerilog, using an index variable j to update and print arr[j] values from 0 to 9 within an initial procedural block.

Learn to perform repetitive array operations in SystemVerilog with repeat, for, and foreach loops; manage an index, assign arr[i] = i, and print the array using arr %0p.

Copy an array into another only when both arrays share the same data type and size, then verify with an elementwise comparison.

Compare two arrays by element to determine equality or inequality, initializing both arrays with identical values and using an equality or inequality operator to set a status flag.

Dynamic arrays in SystemVerilog are sized at runtime with the new method and square brackets; populate with arr[i] = 5*i, print 0,5,10,15,20, then delete to avoid errors.

Explore dynamic array resizing in SystemVerilog: use arr = new [30] to expand storage (clears data), or preserve data by calling with arr in parentheses to copy existing elements.

Compare fixed-size and dynamic arrays by matching size and storage capacity, copy dynamic array contents into a fixed-size array, and see how queues offer efficient access and space.

Explore how queues offer faster access and memory efficiency over fixed and dynamic arrays, declare an integer queue, initialize with 1, 2, 3, and display with %p, no apostrophe required.

Explore queue operations in SystemVerilog essentials, including push_front, push_back, insert at index, delete, and pop_front/pop_back, with practical examples on a fixed and dynamic array-based queue.

Explore using a fixed-size array to model memory in a systemverilog testbench, with a transaction class, write and read controls, an 8-bit address space, and a memory scoreboard.

Learn to use fixed-size arrays, dynamic arrays, and queues in a SystemVerilog FIFO testbench, with a transaction class generating random WData and RData via a generator.

Explore fundamentals of verification, read and build a verification plan from a spec sheet, and apply directed and constrained random tests to a DUT in a layered testbench.

Develop and apply a verification plan for a single-port RAM by listing DUT signals, interpreting waveforms, and defining reset-related test cases to verify core behavior before tackling more complex scenarios.

Learn to craft a detailed constrained random testing plan by mapping spec sections to test cases, signals, goals, and cover groups for scenarios like out-of-bounds write operations.

Compare directed testing and constrained random testing within a verification plan. Learn how cover groups, functional coverage, and scoreboards validate DUT behavior with targeted and randomized tests.

Compare directed testing with constrained random testing through a write operation example, showing how directed tests miss undefined values and corner cases, while constrained random testing targets 100% functional coverage.

Explore the layered testbench architecture and its signal layer, connect components to the DUT, apply stimuli, and verify results across Verilog, VHDL, or SystemVerilog designs.

Explore layer two of the layered testbench, decoding commands from an upper layer into dut signals and applying stimuli, while also translating dut responses back for verification against golden data.

Functions as a scheduling layer, layer three receives stimuli, segregates them into independent commands, and schedules them to layer two for DUT signaling.

Explore layered testbench architecture: layer four generates sequences; layer three schedules commands; a lower level converts a single command to multiple responses; the test layer holds simulation against golden data.

Explore the layered testbench architecture, where the top test layer controls simulation and validates DUT responses against golden data, while lower layers generate sequences and drive commands.

Explore the testbench architecture by examining drivers, monitors, generators, and scoreboards, and learn how environments and IPCs connect them to stimulate the DUT and compare responses to golden data.

Define testbench where a transaction carries DUT inputs and outputs, a generator creates stimuli, a driver applies signals via an interface, and a monitor and scoreboard validate responses with IPC.

Master SystemVerilog essentials by exploring classes, methods, and constructors, and compare function versus task with value or reference arguments, including shallow and deep copy.

Grasp the fundamentals of the SystemVerilog class, declare data members like a 3-bit data and a 2-bit data2, and use a testbench handler to access class members.

SystemVerilog makes classes dynamic objects through constructors, unlike static Verilog modules. Instantiate with f = new and access members as f.data, bit defaults to 0 and reg defaults to x.

Create and use a SystemVerilog class with a constructor to assign values to data members. Access them via a handler and dot operator, then deallocate memory for Marlock testbenches.

Compare adding class methods in SystemVerilog using tasks and functions, highlighting timing control, outputs, and practical uses like constructors and resets in testbenches.

Demonstrates declaring a SystemVerilog function in a testbench with 4-bit inputs A and B and a 5-bit return, including defaults and a printing function, noting timing constructs are not allowed.

Explore how to declare and use a SystemVerilog task, including input and output ports, default directions, and an Adder example, then verify with testbench variables and timing delays.

Explain how pass by value works in SystemVerilog tasks and functions: local copies reside on the function's stack, so main program variables remain unchanged after execution.

Demonstrate pass by reference in SystemVerilog using ref, showing how pointers update variables on the test bench stack and differ from pass by value.

Demonstrate pass by value versus pass by reference with a swap example in a SystemVerilog testbench, showing local copies don’t affect the original a and b after task execution.

Demonstrates pass by reference in systemverilog with ref and automatic storage in tasks and functions, showing A and B swap effects on the testbench and const-based restrictions cause compile-time errors.

Explain the differences between function and task, including timing control, input/output possibilities, and pass-by-reference with ref and automatic storage, plus const access restrictions and common testbench usages.

Pass arrays by reference to avoid copying the array onto the stack. Use automatic init_array with ref, bit [3:0], 16 elements, for loop to initialize and print index and value.

Learn how to add a user-defined constructor in a SystemVerilog class, initialize a data member with or without an argument, and verify by printing its value in a testbench.

Learn how to add constructor arguments for a class with data1, data2, and data3. Use the same names and distinguish them with this keyword to differentiate data members from parameters.

Explore two methods to specify SystemVerilog constructor arguments: by position and by name, initialize data1, data2, data3 (e.g., 23, 4, 35), and access them as f1.data1, f1.data2, f1.data3 with defaults.

Demonstrates initializing multiple constructor arguments by position or by name in SystemVerilog, using the dot operator and this for data members when names clash, with data1, data2, data3.

Learn to implement a SystemVerilog task in a class, call it from the test bench top using F1.display, and display data members data1, data2, and data3 in decimal format.

Learn how to instantiate a class inside another class using a handler, access and modify a data member from the first class, and call its display method to verify changes.

Restrict a data member's scope with local to prevent outside access, then provide a set task and a get function to manage a protected value safely.

Copy the original class data into a new object with a constructor, using P1 = new(F1), so the original remains unchanged and the copy holds the values.

Explore strategies to copy objects in SystemVerilog testbenches by building a custom copy method, sending a copied object to components, and distinguishing shallow versus deep copy for nested data.

Copy data members between class instances in SystemVerilog, first with new and then via a custom copy method, demonstrating independent copies in a testbench and touching shallow versus deep copy.

Demonstrates how a shallow copy duplicates the data member but shares the class instance via a common handler, causing changes to reflect across objects.

Demonstrate shallow copy and deep copy with a simple class example. Show how copying yields independent data members but shares a handler, and how deep copy provides independent handlers.

Explain deep vs shallow copy, showing independent copies of data members and class instances in a deep copy, while shallow copy shares class instances whose changes reflect in the original.

Shows how to implement a deep copy by constructing new objects and copy methods that duplicate data members and handlers, ensuring independent copies.

Create a custom copy method using a task to copy only data members, and compare shallow versus deep copy in SystemVerilog, noting how changes propagate between original and copied objects.

Extend the parent class through inheritance to access its data members and methods, add new members and methods, and enable enhanced stimulus generation and error injection in SystemVerilog and UVM.

Learn how polymorphism works with base and derived classes, virtual methods, and overriding in SystemVerilog to dynamically dispatch the correct display behavior, enabling flexible stimulus generation.

Explore how the super keyword differentiates parent and child constructors in SystemVerilog inheritance, while this distinguishes class data members from arguments, and demonstrates constructor initialization.

Explore randomization in SystemVerilog with rand and randc and learn how constraints, probabilities, and pre- and post-randomization drive transactions and CRCs or parity bits.

Design a SystemVerilog testbench generator that creates stimuli, forwards them to a driver, and tests the dut with constrained random testing across global, data, and control signals.

Demonstrates generating random values for a 4-bit DUT input and a 4-bit Y output using rand and randc, via a generator class and transactions in a testbench.

Master pseudo-random stimulus generation in SystemVerilog testbenches using rand and the randomize method, exploring randc for non-repeating values and for loops for multiple samples of A and B.

Compare rand and randc in SystemVerilog: rand can repeat values, randc cycles through all 4-bit values. Choose rand for repetition, or randc when you want full coverage before any repetition.

Demonstrate checking randomization success in SystemVerilog with if-else and assert, using a status variable. Print status iteratively and signal randomization failure, optionally finishing the simulation.

Demonstrate verifying SystemVerilog randomization using an fs okay block and an assert block, showing expressions, handling success or randomization failure, printing A and B, and issuing finish.

Move the constructor inside the for loop to create a new object for each stimulus. See how the generator, randomize, driver, DUT, monitor, and checker interact in the testbench.

Apply internal systemverilog constraints with the constraint keyword to express simple expressions such as a > 3 and a < 7, and b == 3 or b > 0.

Learn to constrain data signals within ranges in SystemVerilog using inside with curly braces and square brackets, and verify non repeating randc values for a and b.

Add constraints to skip ranges in SystemVerilog, excluding 3–7 for a and 5–9 for b, using a single constraint block and the not operator.

Learn to define constraints and methods outside a class using extern and prototypes, with class scope references and examples for a and b ranges.

Explain how pre_randomize and post_randomize work in SystemVerilog, showing how to set min and max constraints before randomization and print a and b after successful randomization.

Explore how randc creates a bucket of values from a constraint, generates random values, and how changing constraints at runtime resets the bucket and may cause repetition.

Set up two randc spaces by adjusting constraints, generate six random samples per space, and observe how changing min and max affects value repetition across spaces.

Understand weighted distribution in SystemVerilog constraints to bias a rand write signal toward 1 over 0, using the : equals to operator and weights like 10 and 90.

Compare two distribution operators in SystemVerilog: one assigns equal weight to all values in a range, the other divides weight evenly between them, illustrated with a 2-bit select.

Explore weighted distribution in SystemVerilog p3, assigning 0 a weight of 10 and distributing 60 across the range 1–3, comparing equal weight to a range with equal division within range.

Explore how to apply the weighted distribution operator in a SystemVerilog testbench by defining read and write signals, constraints, and a pseudo-random number generator to print results comparing operator behavior.

Explore weighted distributions in SystemVerilog using rand with two 2-bit variables v1 and v2. Analyze how per-value weights and iteration count reveal probabilities and why an operator yields closer weights.

Explore SystemVerilog constraint operators: implication, equivalence, and if, detailing how X implies Y and how X and Y must match, with examples.

Demonstrate the implication operator in a SystemVerilog testbench, enforcing that reset zero keeps chip enable high while reset one allows variation, using a constraint block with 80/20 weighting.

Explore how the equivalence operator enforces mutual exclusivity between write and output enable in a memory, using 50/50 randomized constraints and a test bench.

Explain how the if else operator governs memory write and read sequences, with write addresses 11 to 15, read addresses zero during write, and verifying data on readback.

Disable and selectively enable constraints to test stimulus generation in SystemVerilog, using a constraint mode to switch constraints on or off and verify their active status during simulation.

Develop a fifo testbench by implementing a transaction and a generator class for a fifo dut, using clock, reset, write and read requests, w data, read data, and full/empty flags.

Build a SystemVerilog transaction class to encapsulate signals like write request, read request, and data buses, choosing bit or logic states and applying constrained random testing for global signals.

Explore interprocess communication techniques in SystemVerilog essentials, using events, semaphores, and parameterized mailboxes to safely send data between generators, drivers, and DUTs.

Explore interprocess communication in SystemVerilog by comparing events, semaphores, and mailboxes, including edge and level sensing, get and put methods, and blocking versus non-blocking operations.

Explore interprocess communication in SystemVerilog, using events to signal completion and semaphores or mailboxes to exchange data between the generator, driver, monitor, and scoreboard in a testbench.

Declare and trigger events in SystemVerilog to convey messages between classes. Use the -> operator to trigger and @ or wait for edge sensitive and level sensitive sensing.

Compare edge-sensitive @ and level-sensitive wait operators in SystemVerilog by triggering events A1 and E2, showing blocking vs non-blocking behavior and how delays affect event sensing.

Explore how a SystemVerilog testbench uses independent tasks for generator and driver to create and apply stimuli to a DUT, while monitors and scoreboards operate in parallel using blocks.

design a pure verilog testbench with a generator and driver running in parallel, using urandom, data1/data2, a 10 ns delay, and a done event to emit 10 stimuli.

Explore using a fork-join to run multiple initial blocks in parallel in SystemVerilog, with independent tasks for generator, driver, and simulation control, finishing when all stimuli are generated.

Master forking and joining multiple processes in SystemVerilog using fork join variants and initial blocks. Generate 10 random 8-bit stimuli with a 10 ns delay and synchronize generator and driver.

Explore how to use fork join to run generator, driver, monitor, and scoreboard in parallel, synchronize data exchange with events, and avoid race conditions in SystemVerilog testbenches.

Illustrates fork-join with parallel tasks and delays of 20 ns and 30 ns, printing start and completion times, and demonstrates that post-join code runs only after all tasks finish.

Explain how fork join with join_any allows proceeding as soon as any one process completes, unlike fork join that waits for all processes to finish.

Explore fork join_none in SystemVerilog, a purely non-blocking construct that starts task1 and task2 at zero and proceeds without waiting, unlike fork join or fork join_any.

Explain how to use fork join to run generator, driver, monitor, and scoreboard tasks in parallel within a verification environment, and compare fork join_any versus fork join for synchronization.

Demonstrate semaphore-based access control between two data writers, using a single semaphore to serialize writes, with get and put operations, random data under constraints, and fork-join coordination.

Explore how a mailbox enables sending data from a generator to a driver using mbx and the put and get methods to transfer a value 12 and communicate the event.

Learn to implement a SystemVerilog driver with a shared mailbox, create a data container, and establish a generator and driver data path in a testbench top for synchronized data transfer.

Add a custom constructor to specify a shared mailbox between generator and driver, using mbx, simplifying testbench wiring and ensuring the same mailbox is used between generator and driver.

Generate and send 10 random transactions via a mailbox in a SystemVerilog testbench, using a simple transaction class with two 4-bit inputs and a 5-bit output.

Explore sending transaction data via a mailbox between generator and driver in SystemVerilog, using a transaction data container, the get method, and showing din1 and din2 with 10 ns delay.

Parameterize the mailbox with the data type to enforce transaction data across generator, driver, monitor, and scoreboard, using a transaction class and # syntax to declare mailboxes.

Declare a mailbox and data container to receive data from the generator, use a parameterized mailbox between the generator and driver, and access the transaction data via the do_data member.

Learn how parameterizing a mailbox enforces type safety by permitting only transaction-type data in put, and throws an error for incompatible types like logic [7:0], guiding testbench design.

Specify the data type on a parameterized mailbox when operating on a transaction to catch data type mismatches and ensure correct mbx usage in generator, driver, and testbench top.

Explore using interfaces and modports to drive a DUT from a class, and access the interface in both class and module, then create generator, driver, monitor, and scoreboard components.

Explore the fundamentals of interface design in SystemVerilog for interprocess communication, linking signals and resources between classes and the DUT, using events, semaphores, and mailboxes to build a testbench.

Declare a SystemVerilog interface for an adder, using logic ports and a 5-bit sum. Show data flow from interface variables to DUT and testbench drivers to drive and monitor results.

Create an interface instance in the testbench, connect it to the dut with positional or named port mapping, and access interface members like a, b, and sum via dot operator.

Apply stimuli to interface signals aif.a and aif.b, comparing blocking and non-blocking operators. Verify the DUT output with a VCD dump showing 3+4 equals 7.

Demonstrates why blocking assignments can drop intermediate values when signals change between clock edges in an interface, using a synchronous adder and clock initialization.

Learn to use non-blocking assignments for interface variables and clock-edge delays, applying repeat for multiple clock ticks to ensure stable values in a SystemVerilog testbench.

The lecture explains why using logic in interfaces over reg or wire avoids procedural and continuous assignment conflicts, enabling proper input stimulus and output responses for SystemVerilog designs.

Add driver code to an interface to drive a dut adder with stimuli using adder_if; connect through tb, generate a 20 ns clock, dump waveforms, and run for 100 ns.

Create and instantiate a driver with a constructor, connect its interface aif to the test bench, and drive stimuli to the dut using non-blocking assignments and a do_run task.

Explore modport in SystemVerilog to enforce direction constraints in interfaces, preventing wiring errors between driver and monitor by restricting A, B, sum, and clock directions.

Add a generator and a transaction class to a system-level systemverilog test bench, modeling a two-state A, B, and sum, with randc for A and B and a display method.

Explore building a systemverilog generator that transmits ten randomized transactions via a mailbox to a driver, highlighting single-object versus per-iteration object creation and data integrity challenges.

Learn to build a generator-driven test bench in SystemVerilog by using a transaction class with randc, a mailbox for data transfer, and deep copy to maintain history for independent objects.

Add the transaction constructor in the generator's custom constructor to maintain a history of data and use a deep copy between generator and driver to keep test bench timing independent.

Add a generator with a deep copy of transactions using a copy method and a mailbox between generator and driver, enabling synchronized random transaction generation and display in SystemVerilog.

Declare a done event to sync the generator with the testbench stop via a mailbox, then use a non-blocking fork-join and wait for the event to trigger before finishing.

Create a single transaction with a generator constructor to preserve history and RandC behavior. Send deep copies to the driver to make iterations independent and enable error injection.

Extend the transaction class to inject an error by constraining a and b to zero. Connect the error object to the generator and verify the driver receives zeros.

Explore injecting errors in a SystemVerilog testbench using an error injector that extends the transaction and overrides methods to modify generated data via constraints or a virtual method.

Sample DUT responses in a monitor; send them to a scoreboard via a transaction class over interface; apply 20 stimuli to A and B with a for loop and urandom_range.

Create a monitor class with a mailbox and a transaction object to send data to the scoreboard via a virtual adder_if on posedge, updating trans.a, trans.b, and trans.sum.

Create a scoreboard class that receives data from a monitor via a mailbox and transaction, prints the values to the console, and verifies data flow in the testbench.

Delay stimuli and sampling by one or two clock ticks to synchronize the monitor and scoreboard with the DUT, then validate with console outputs and waveforms.

Develop a simple scoreboard model by sampling monitor data and DUT outputs, comparing A plus B to sum, and using error, warning, or fatal to flag mismatches.