Communication Series P1 : UART, SPI and I2C in Verilog

Learn how spi operates as a four-wire, full-duplex synchronous interface where the master drives the clock, data timing, and chip select, covering mode zero and other modes with edge sampling.

Understand the fundamentals of spi, including four pins (s clock, mosi, miso, slave select) and master-driven transactions, with msb-first data across 8–32 bits.

Explore SPI modes, polarity and phase definitions, and how clock edges determine data sampling; learn to implement mode 0–3 in a Verilog SPI interface.

Understand spi timing variability across devices, including chip select, s clock, mosi, and miso, and learn to wait a single s clock cycle before transmitting data in verilog on fpga.

Implement a simple SPI master with single mode, transmitting eight bits on the positive edge and sampling on the negative edge of a slower S clock, framed by chip select.

Build an 8-bit SPI master using an FSM with idle, start_tx, tx_data, and end_tx states. The module generates s_clock, asserts chip_select, and transmits data on MOSI when tx_enable is high.

This Verilog SPI master uses a two-process design to manage reset, idle, start TX, and TX data, controlling mosi, chip select, and s_clock via a next-state decoder.

Explore a Verilog SPI master demonstration: reset and tx_enable sequencing, chip select control, eight-bit data transmission on s_clock, and sampling on the negative edge toward a slave design.

Design an spi slave that samples 8-bit data on the negative edge of s_clock when chip select is low, using idle and sampling states with a left-shift register and done signal.

We build a testbench for the SPI slave by generating clock, reset, and enable stimuli and verify the master's data appears as A and then F.

Explore alternate spi master implementations using an fsm on the s clock. Understand clock generation from system clock, reset, tx enable, chip select, and 8-bit msb-first data transmission.

Understand CPOL behavior in a Verilog SPI interface, exploring idle S clock values and edges across modes 0–3 with S clock at 1/4 F clock for 8 bits.

Generate a serial clock four times slower than the system clock to drive a 16-edge SPI transfer; manage start, ready, polarity, and a 2-bit clock counter for edges.

Explore how CPHA defines the slave sampling edge in SPI, clarifying mode zero to mode three, polarity, phase, and data stability on the MOSI bus around clock edges.

The lecture explains SPI modes 0–3, detailing how CPOL sets the clock polarity and CPHA determines sampling edges, with data must be stable before each edge and the MOSI timing.

Execute an SPI master flow using cphase to start transmission on the first or delayed edge, while controlling chip select, MOSI data, and a five-state FSM.

Explain mode zero SPI, with C polarity and C phase at zero, so S clock idles at zero. Show MOSI data held for half a clock around the sampling edge.

Explore how a spi slave detects start of transmission, samples 8-bit data on the s clock, and left-shifts bits into rx data with chip select and mode-dependent edges.

Explore how a Digilent PMOD DA4 DAC uses SPI to select a DAC via a 4-bit address, send 32-bit commands, and instantly update the DAC channel with 12 data bits.

Design a master SPI controller to drive the PMOD DA4 DAC, initialize the DAC, generate a slower s clock from the 100 MHz clock, and serialize a 32-bit data word.

Showcases spi data transfer from a Verilog dut, generating 100 mhz and reducing to 1 mhz for simulation, sending 32 bits via mosi with s clock and chip select.

Implement daisy chain configuration in SPI to reduce extra chip select pins by linking slaves in a serial data path, with data passing from one slave to the next.

Operate the master to transmit 8-bit data on SGO using chip select and a serial clock at 1/8 the input rate, while concurrently receiving data via another FSM.

Design and implement a slave that handles master transactions via two FSMs, 8-bit shift registers, and a new data flag in a daisy chain SPI configuration with a test bench.

Shows a Verilog testbench for an SPI master–slave system, generating clocks, driving new_data, and transmitting 8-bit data, with two FSMs handling transmit and collect in a two-slave daisy chain.

Explore I2C fundamentals, master-slave communication with two wires, clock synchronization, and 7-bit/10-bit addressing, including write/read operations, clock stretching, and Verilog implementation.

Understand how I2C uses open drain on SDA and SC lines with pull-up resistors to produce one, while masters pull low for zero, implemented in Verilog with SDA inout.

Master the I2C start and stop conditions using SDA and SC signals, with a four-part bit duration waveform showing address, acknowledgment, and data transfer.

Describe i2c write and read transactions, including start condition, 7-bit address with r/w bit, ack/nack, data bytes, optional register address, and stop condition for memory or sensor peripherals.

Implement an I2C master finite state machine without clock stretch, handling start, slave address and operation type, address bits, acknowledgments, read and write data, and clean stop sequences.

Explore implementing an I2C master without clock stretching, handling SDA and SCL signals, 7-bit address with read/write operations, 8-bit data, acknowledgments, and an 8-state FSM from start to stop.

Demonstrates a testbench for an I2C master, including modified master behavior, manual acknowledgments, and serial write of address and data with clocked SDA control and start/stop sequencing.

Develop an i2c slave memory that understands master transactions and provides memory data for the master, using 128 eight-bit locations and synchronized start conditions with d_out for reads.

simulate a testbench for top that runs i2c master-slave transactions with 10 writes and 10 reads, printing din, address, and dout to verify correct data transmission and handshake.

Learn how to bit-bang SPI transactions on Arduino using GPIO pins, driving chip select and clock signals to send data without a dedicated SPI controller.

Learn how clock stretching lets an I2C slave pause the master by pulling the SCL line low during acknowledgment, and how to implement this in the controller's acknowledgment state.

Implement the master in Verilog by releasing the SCL line, reading rscl to detect clock stretching, and generating clocks for write and read while handling acknowledgment on the SDA line.

Modify the slave logic to handle clock stretching via a wait stretch state. Demonstrate normal operation and stretching scenarios, showing memory updates occur consistently.