CMOS VLSI - Fundamentals, Design & Technology

In this session, we will have an introduction of the VLSI technology. We will learn about the evolution about the transistor count, clock frequencies and power requirement in today's IC design process. We will also see how technology node/process has evolved in the past few decades. We'll make comments about Moore's law.

Learn

• MOS transistor semiconductor physics. 

• MOS transistors (NMOS and PMOS) principle of operation.

• CMOS transistors as switches.

• CMOS transistors as a logic gates and latches.

• Learn how CMOS transistors are mass produced on silicon wafer called substrate.

• Learn different masks used to fabricate a CMOS transistors (top and cross-section view) .

• Learn why modern gate of MOS transistors are made of silicon(poly).

we see how to implement cmos compound logic. The role of Pull-down and Pull-up explained.

This session starts with the quiz and its answer. We get a few exercises on the design of the combination logic using CMOS transistors. We learn how to construct a cmos circuit from the given boolean function and vice-versa.

We explore past gates and its importance.

We see how to build non inverting functions using CMOS gates

We introduce a tristate buffer/inverter, multiplexer and we learn how to create mux using tristate logic, pass gate and compound logic transistors

We learn more about the pass transistors. We understand what the degraded logic is and we learn about the best practice/mentd to design a cmos logic.

We introduce a sequential circuits/logic

We learn about cmos D-latch and its use, timing diagram.

We then introduce flip-flop, its operation in master-slave mode and timing diagram

We continue explaining the difference between a latch and a flip-flop.

We introduce the CMOS fabrication process (basic), where we talk about the different masks used in fabricating a cmos inverter circuit. We explain step-by-step how different parts of the IC will be fabricated. A top view and the side-view of a cmos inverter is shown the way it will be fabricated

You will learn different steps used in the CMOS fabrication, about different masks used, photolithography, wafer, etc.

This session continues with the CMOS fabrication steps and the related concepts of fabrication.

We then introduce layout design rules used in IC fabrication. With the example, we learn how to use different layers in the CMOS process and understand limitations.

Here, we learn more about IC layout rules and understand parameters such as MOS transistor width/length ratio. We understand deeper concepts of the layout, and start drawing the layout of the basic unit cells such as Inverter, NAND, NOR, etc.

We introduce the concept of a stick diagram to draw the layout. Using a stick diagram we introduce a few layout examples and summarise the layout session.

Next, we explain what is design partitioning in IC design, and we provide an overview of an IC design process through a block diagram. You will know and understand the different departments better. You will know about details on system specifications, architecture design, functional/logic design, circuit, physical design and verification, fabrication, packaging and test .

We learn what the hardware description languages (HDLs) are and how they are used. We understand what the logic simulator is , what the logic synthesizer is and other tools used by the VLSI hardware industry in the chip design process.

Here, we continue with the concepts on SoC/ASIC implementation. We take an example of a microprocessor design and explain how SOC's/ASIC's architecture, microarchitecture, logic, circuit, layout, verification will be carried out by the engineering design teams that are assigned this chip design job.

We also learn how HDLs are introduced to implement logic and tools used for it.

In this one of the most important sessions, we learn about power and delay in CMOS circuit design. We understand the MOSFET model and understand dealy in CMOS logic (through CMOS inverter example). We learn how to reduce the delay in a circuit.

We then understand power in a CMOS logic/circuit, and how to reduce power consumption.

We learn how EDA tools (synthesis) help us to auto-build circuits optimised for power and delay.

We introduce the concept of netlisting. We will learn how verilog and SPICE can be used to generate structural and/or transistorised netlists that will be used by the layout engineering team.

This session continues with the netlisting using Verilog and SPICE. We explain this through examples.

Next part is to understand the concepts of floorplan, and how the processor layout is implemented. An example is given.