CMOS Digital VLSI for Beginners

This lecture contains MOS structure basics, an Energy band diagram under zero bias conditions, and the concept of Flat band voltage.

This video contains two terminal MOS structures operating under different bias conditions. Depending upon applied gate voltage, accumulation, depletion, and inversion occur. These phenomena are explained with the help of a band diagram. Depletion layer charge calculation is provided in the resource file.

Threshold voltage and its components, Body bias effect, Threshold voltage adjustment using channel ion implant technique. solved problem related to threshold voltage estimation and channel ion implant calculation is provided in the resource file.

Drain current calculation using gradual channel approximation technique

Channel length modulation effect and modification in drain current due to CLM effect

Introduction to MOSFET Scaling. Constant Field scaling and its effect on drain current, power dissipation, power density, and Gate capacitance. Problems associated with constant field scaling

The effect of constant voltage scaling on drive current, power dissipation, power density, and gate capacitance is discussed.

Different 2nd-order non-ideal effects in submicron MOS transistor is discussed.

Introduction to MOS inverter, Voltage transfer characteristics (VTC), Critical voltage points, Noise immunity and noise margin.

Circuit diagram and operation of resistive load inverter, Voltage transfer characteristics, Variation in VTC curve for different load resistance values. calculation of output low (VOL) value for resistive load inverter,

MOS inverter with active load is discussed. The major drawback of a resistive load inverter is a larger area requirement and high power dissipation. The passive resistance in the resistive load inverter is replaced by one active MOS device.

The DC characteristics and operation of CMOS inverter are discussed with analysis and derivation. Condition for symmetrical CMOS inverter is derived.

Transient operation of CMOS inverter and definition of delay times.

Delay calculation using average current approximation method.

Delay calculation by solving state equation.

A super buffer is a chain of inverters used to drive a large capacitive load connected at the output of any logic gate/device. Instead of drastically increasing the device size, the transistor size inside buffer gradually increases by some factor ALPHa so that the load capacitor can be driven with minimum delay. In this section, detailed construction of super buffer is discussed and calculation of optimum scaling factor ALPHA is demonstrated.

Super buffer design-part 2

Super buffer design part-3

Different power dissipation components in CMOS circuits.

Introduction to CMOS Logic design. CMOS logic consist of NMOS and PMOS network called pull down and pull-up network. The function of PMOS network is to charge the load capacitance to logic-1 i.e. VDD and NMOS network i.e. pull down network is used to discharge the capacitor to logic-0 i.e ground.

CMOS NAND and NOR gate implementation

Realization of Boolean function using CMOS logic

Lambda and Micron rule is discussed. Concept of stick diagram and layout is discussed.

This lecture discusses steps to designing a stick diagram of the CMOS inverter, CMOS NAND, and NOR gate.

Introduction to Dynamic CMOS logic. The construction and working mechanism of dynamic CMOS logic or precharge-evaluate logic has been discussed. The advantages of dynamic logic circuits are explored.

Discussing regarding cascading issues in dynamic logic circuit.

Solution of cascading problem-DOMINO Logic

Charge sharing problem in dynamic circuits and its solution

NP DOMINO or NORA logic circuit operation

Introduction to pass transistor. NMOS and PMOS as pass gate.

Implementation of two variable and three variable Boolean function using pass transistor.

CMOS Transmission gate logic