I completed dual degree in vlsi from IIT Madras in 2013 and started working as a physical design engineer in TSMC, Taiwan. I moved to Qualcomm, Bangalore in 2017 and currently working as a senior engineer, responsible for SOC integration. I have worked in 20+ tapeouts and 7+ are in advanced 7 nm. I have developed flow for PNR, STA, PV and also have developed html based results viewing environments. I love to solve the issues faced in Physical Design field. It's always an interesting debug!!!