Building Processor with VHDL from Scratch

Explore the logical unit by detailing verilog logical operators, constrain opcode decoding, and add the unit to the rtl, followed by a testbench to verify operation.

Extend the processor with a four-bit logical unit in VHDL, perform bitwise operations (and, or, not, nand, nor, xor, xnor) on a general purpose register, and verify results.

Add a logical unit with unique opcodes for or (5), xor (7), nor (8), nand (9), and not (11); implement mode selection to choose between immediate data and register operands and update destination register.

Test logical operations on the processor using oring and anding with immediate data, then xor, verifying results in gp4, r5, and r6 via the testbench and opcodes 00101 and 00110.

Explore building sub programs in VHDL using functions and procedures to manage multiple outputs, illustrated through an instruction decode process and register updates.

Learn to declare and use a VHDL procedure for addition, including input parameters, signal vs variable types, and connecting architecture signals to procedure ports.

Convert the instruction decode and execute process into a procedure named instruction execute, wiring a 32-bit instruction register, gpr, add and multiply results, and sg.pr, then verify with a testbench.

Add a condition flag to control flow in the processor, guiding the next instruction address for jumps and branching. Understand, implement, and test different condition flags through code.

Explore condition flags usage in an ALU output, including sign, zero, carry, and overflow flags, and how they guide subtraction, comparisons, and addition operations.

Learn to add carry, sign, zero, and overflow flags (with parity to come) to enable jumps and complex algorithms in a processor, illustrated with VHDL sizing.

Explore how the overflow flag detects invalid results in addition and subtraction by examining input combinations and the MSB of sources and results, including immediate mode handling.

Explore how the sign flag uses the MSB to indicate negative values, and how the zero flag is derived differently for multiplication (32-bit results) versus other operations via OR reductions.

Introduce an impure function to compute a four-bit condition flag vector (sign, zero, carry, overflow) from the instruction result, then map it to the processor's individual flags.

Demonstrates verifying condition flags by adding stimuli that trigger zero, carry, sign, and overflow in a VHDL processor. Shows moving values to set MSb, performing additions, and observing flag changes.

Add program and data memory, explore von Neumann, hardware, and modified hardware architectures, and compare FPGA strategies using IP blocks or Verilog arrays, then test memory with a program.

Learn how to add memory to a processor for data and instruction storage, comparing von Neumann bottleneck with hardware architectures featuring independent data and instruction memories and independent buses.

Add a 64-location, 32-bit program memory and data memory to processor p1, loaded from a file via VHDL using load_program at operation start.

Add program memory and data memory to processor P2, run the simulation, and verify the first program memory instruction equals 08010003 before feeding it into the instruction register.

Read, decode, and execute instructions from program memory. Update the program counter and condition flags using a 1D array for data memory and six-clock delay counter for 32-bit instructions.

Add a testbench to verify a processor with program memory by generating reset and clock stimuli, then load the program and execute instructions, observing the condition, overflow, and carry flags.

Learn to extend a vhdl processor with 16-bit data memory access, input/output buses, and store and send instructions to interact with external world.

Develop and verify data memory and i/o port operations in a VHDL processor with a testbench, storing r14 to memory address zero and driving data to the d out bus.

Implement jump and branch instructions using condition flags to control program flow in a VHDL processor. Write, test, and verify the control unit with a complex program.

Learn how the processor implements jump and branching instructions, including eight branching options based on sign, zero, carry, and overflow flags, and a direct 16-bit address for program memory.

Explore direct jump and branching instructions: update the program counter to the jump address; use jump zero when the zero flag is set; jump no overflow when reset.

Implement jump and halt operations in a VHDL processor by using flags to drive jump decisions and a stop flag to halt, with immediate addresses and a decode-execute procedure.

Extend the processor by adding unique opcodes for jump and halt (jump code 1010) and initialize jump and stop flags within the decode-execute flow.

Enhance the FSM to support jump and halt by adding jump and stop flags and new states, updating the program counter and instruction memory flow.

Verify that the jump instruction, with opcode 10010, resets the program counter to address zero after finishing 13 instructions, using behavioral simulation and a reset.

Verify the halt instruction using opcode 11011 to stop execution and freeze the program counter after the condition flags update; reset or power removal restarts from the first instruction.

Demonstrates testing of branch instructions by simulating multiplication of five and six using repeated addition, with six iterations, zero flag, and jump if not zero, culminating in a halt.