Building a RISC-V SoC From Scratch!

Explain how processors read data in binary or hexadecimal, perform operations, and write results to registers or memory, using a five-stage pipeline—from fetch to write back.

Explore the risc five instruction set architecture, its 32-bit words, and diverse instruction types like R-type, I-type, S-type, and J-type, plus extensions and compressed instructions.

Explore how to write assembly instructions, manipulate registers and memory with load and store operations, and use immediate values, addressing, and branching in a hands-on lab.

Understand how a RISC-V compiler converts C code to machine code, how the linker and linker scripts assemble object files into an ELF executable, and map code into memory.

Master linker scripts through an online risc5 assembler, connecting assembly and C code via .text, .data, and .bss sections. Build hands-on understanding of memory layout, heap, and stack.

Install the OS cat suite on Linux Ubuntu 18, set up the riscv toolchain, and configure VS Code with the HDL extension for Verilog development.

Engage in a hands-on lab to design a picoRV32 based SoC, connect the processor to memory, and visualize how instructions drive memory transactions on the bus using the Risc5 compiler.

simulate the basic SoC with Icarus Verilog by compiling Verilog and hex files, then generate waveforms with GTKWAVE to observe processor–memory communication and the trap-based termination.

Learn to program the SoC in C with a makefile that automates compilation, linking, and binary generation, and see how the start routine initializes the stack and drives leds.

Add a gpio peripheral to a RISC-V SoC using a simple bus and address decoding. Map a 32-bit register at 0x44000 to control external LEDs.

Design a compact, modular gpio peripheral for a riscv SoC using Corsair to auto-generate memory-mapped registers, Verilog, and C headers, enabling led control.

Learn how the Corsair register map generator creates Verilog for an advanced GPIO, install on Ubuntu 22, and configure a 32-bit register at offset zero with a local bus interface.

Integrate the Corsair GPIO Verilog into the SoC, modularize the top level, and test the GPIO interface using Corsair-generated headers with simulation.

Explore the Uart core enabling simple serial communication with a host PC, transmitting eight-bit bytes at a configured baud rate using a three-register interface: data, status, and control.

Explore the uart transmitter interface in a riscv soc from scratch lab, configuring clock frequency and baud rate, and streaming 8-bit data with input valid and output ready signals.

Integrate the uart into the soc, align the register map, and write software while simulating to validate the uart integration and prepare for emulation.

Understand the FPGA design flow from Verilog entry through synthesis, mapping, placement, routing, and timing analysis to bitstream generation for programming the Gowin little B FPGA in a risc-v SoC.

Program the FPGA and observe real-time LED blinking and host PC communication. Tune the build, run synthesis, place and route, assign pins, program with bootie, and verify UART output.