
Learn how the processor performs add, subtract, and multiply in immediate and register modes, using move and move sgpr to handle a special register for 32-bit results.
Define unique operation codes for or, and, xor, xnor, nand, nor, and not, then implement RTL logic for immediate and register modes, including complement with a testbench.
The testbench verifies logical and and or operations in immediate mode, then xor, using gpr4 as destination, gpr7 as source, and 56 as immediate, printing operation type and register values.
Compute the zero flag by ORing all bits of the result and taking the complement; for multiplication, OR sgpr (MSB 16 bits) with the LSB 16 bits, then complement.
Apply stimuli to verify zero, sign, carry, and overflow flags by manipulating GPR 0 and GPR 1 with addition, including 0, 0x8000, and 0x8002 values, and observe flag responses.
Replace independent always blocks with tasks in Verilog to decode_instruction and decode_condition_flag, and add ports while converting both blocks to endtask-based tasks.
Add jump and branch instructions using condition flags by building an FSM control unit to manage program flow. Discuss supported instructions, implement the code, and test with a complex program.
Learn how direct jump updates the program counter to the address specified in the instruction, and how branching uses zero or overflow flags to decide whether to jump or proceed.
Develop a Verilog HDL processor RTL with jump instructions and a jump flag system. Explore conditional jumps using zero, carry, sign, and overflow flags, and halt to control program counter.
Designs a verilog rtl fsm using parameterized state names for idle, fetch, decode, delay, predict, and sense halt, controlled by a three-bit state variable.
Most of the 21st-century applications require powerful hardware but also along with the centralized controller allowing the development of complex algorithms. As we enter into the AI or Cloud-based devices and as systems complexity is growing daily, the need for incorporating multiple processor instances becomes mandatory as we progress in the AI era. Zynq and Microblaze are two popular alternatives that exist in the market suitable for almost any application requirements. The requirements of using Multiple instances of Processor viz. Multiple instances of Microblaze soft processor or using a hard processor such as Zynq Processor along with single or multiple instances of Microblazer become necessary to independently handle both Data processing and control requirements. The fundamental challenge of incorporating multiple instances of Soft processors like Microblaze is the number of resources consumed for implementing Microblaze on the FPGA. Since FPGA consists of a limited amount of the FPGA resources, hardware and Software partition plays a prominent role in building complex systems. Another popular alternative approach followed by Embedded Engineers to build a Custom CPU / Processor with the only required functionality thereby saving a large amount of the resources as compared to adding Microblaze instance. The course will discuss all the fundamentals required to build a simple processor/ CPU with Verilog HDL and strategies to test its functionality. After completing this course, you will understand all the necessary skills required to build Complex CPU architecture to meet requirements. Best wishes for crafting your own processor.