Building a Processor with Verilog HDL from Scratch

We will outline the logical unit and Verilog operations, balance operator use with limited opcode decoding space, and integrate the unit into the rtl to verify it with a testbench.

Explore adding a logical unit to the processor ALU, implementing Verilog bitwise operators (AND, OR, XOR, XNOR) and NAND, NOR, and NOT, with two-source and immediate addressing in RTL.

Define unique operation codes for or, and, xor, xnor, nand, nor, and not, then implement RTL logic for immediate and register modes, including complement with a testbench.

The testbench verifies logical and and or operations in immediate mode, then xor, using gpr4 as destination, gpr7 as source, and 56 as immediate, printing operation type and register values.

Analyze the rtl output by executing the code and observing 8-bit destination, source, and immediate data, verifying both and xor operations yield the expected results, and prepare for conditional flags.

Add and test the processor's condition flag to enable jumps and branches, explain supported flags and their operations, implement the rtl code, and verify with a test program.

Explore how to implement sign, zero, carry, and overflow flags for the ALU output in a Verilog processor, with parity flag design as future work to support branching operations.

Implement the carry flag in a Verilog HDL processor by adding two 4-bit inputs to produce a 5-bit result and using the MSB as the carry.

Analyze overflow logic for addition and subtraction, using input MSB and result signs to form conditions, and derive carry, sign, and zero flags.

Explore how the sign flag equals the MSB of the result in two's complement, and how the zero flag is the negation of the OR of all bits in Verilog.

Initialize four flags and compute the sign flag in a combinational always block; for multiplication, use sgpr MSB, otherwise use the destination register MSB for addition or subtraction operations.

Implement the carry flag by adding 16-bit inputs and using a 17-bit temp_sum. Generate carry from the most significant bit of temp_sum for both immediate and register addition, otherwise zero.

Compute the zero flag by ORing all bits of the result and taking the complement; for multiplication, OR sgpr (MSB 16 bits) with the LSB 16 bits, then complement.

Determine and implement the overflow flag for addition and subtraction in rtl, handling immediate and register modes by evaluating msb bits and complements, and verify all flags with a testbench.

Apply stimuli to verify zero, sign, carry, and overflow flags by manipulating GPR 0 and GPR 1 with addition, including 0, 0x8000, and 0x8002 values, and observe flag responses.

Add program and data memory in an FPGA, compare von Neumann, Harvard, and modified Harvard architectures, and implement memory with Verilog arrays, then test with a program.

Compare Von Neumann and Harvard memory architectures, then examine data memory and instruction memory with independent buses and the modified Harvard approach, before implementing a Harvard-based processor in Verilog HDL.

Compare memory generator ip and verilog arrays to implement program memory and data memory, then configure a block memory generator, create a coe file, and integrate with verilog/vhdl.

Declare a 32-bit memory array M with 16 elements, load it from a .mem file using readmemh, and feed M[count] into the instruction register every four clock ticks.

Add program and data memory to the processor with Verilog arrays; implement 32-bit instruction memory and 16-bit data memory in a Harvard architecture, plus clock, system_reset, DIN, and output_data.

Replace independent always blocks with tasks in Verilog to decode_instruction and decode_condition_flag, and add ports while converting both blocks to endtask-based tasks.

Load instruction memory from instruction_data.mem with readmemb, then after a four clock tick delay, increment program counter and decode the next instruction into the instruction register using decode_instruction and decode_condition_flag.

Add four data memory instructions—storeReg, storeDIN, sendDout, and sendReg—to interact with data memory via the DIN and Dout ports, using GPRs and 16-bit immediate addresses.

Develop a testbench to feed program memory with instructions and verify arithmetic, logical, and store operations. Convert each instruction to ones and zeros and load them using readmemb and readmemh.

Learn to add a testbench for a Verilog RTL processor, declare ports as reg and wire, generate a clock, apply reset, and observe registers and data memory in simulation.

Add jump and branch instructions using condition flags by building an FSM control unit to manage program flow. Discuss supported instructions, implement the code, and test with a complex program.

We cover jump and branching, with direct jumps to memory and eight flag-based branches using sign, zero, carry, and overflow; encoding uses five msb opcode bits and 16 lsb address.

Learn how direct jump updates the program counter to the address specified in the instruction, and how branching uses zero or overflow flags to decide whether to jump or proceed.

Develop a Verilog HDL processor RTL with jump instructions and a jump flag system. Explore conditional jumps using zero, carry, sign, and overflow flags, and halt to control program counter.

Expand the FSM to handle jump, branch, and halt by fetching and executing instructions, updating the condition flag, applying a four-clock delay, and predicting next address with the jump flag.

Designs a verilog rtl fsm using parameterized state names for idle, fetch, decode, delay, predict, and sense halt, controlled by a three-bit state variable.

Test the updated FSM against the existing program to verify register values and data memory interactions, confirming addition, multiplication, oring, and nanding results still load correctly.

Demonstrate Verilog HDL verification of jump and branch instructions by implementing a 6 by 5 multiplier via repeated addition, tracking iterations with r3 and tallying results in r2 and r5.

Execute a behavioral simulation of processor in verilog hdl, observe jump and zero flags, verify R3 becomes zero and R2 and R5 show 30, with halt signaling stop.