Become Zero to Hero in vlsi design [comprehensive video]
2.8 (3 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
2,051 students enrolled

Become Zero to Hero in vlsi design [comprehensive video]

This course this totally about vlsi design practical approach and its related other thing which is basic for design vlsi
2.8 (3 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
2,051 students enrolled
Created by Sanjeev Kumar
Last updated 11/2019
English
Current price: $13.99 Original price: $19.99 Discount: 30% off
5 hours left at this price!
30-Day Money-Back Guarantee
This course includes
  • 4.5 hours on-demand video
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • The students are going to learn about physical design, the very essential process to make an integrated chip. This process of physical design consists of various steps and all of them are interrelated.
  • We have design this video lecture to provide students an in-depth exposure to the subject with clarity that none of the material is out of prescribed syllabus.
  • Each part has consisted brief but necessary information with the entire requisite.
Requirements
  • yes ,the student should have very basic knowledge of electronics, physics and math.
Description

The design and optimization of integrated circuits (ICs) are essential to the

production of new semiconductor chips.

The design-cycle of VLSI-chips consists of different consecutive steps from high-

level synthesis (functional design) to production (packaging).

The physical design is the process of transforming a circuit description into the

physical layout, which describes the position of cells and routes for the

interconnections between them

Physical design produces an Integrated chip for used in application ranging from

military ,consumer appliances, entertainment gadget ,mobile and so on.

The main concern in the physical design of VLSI-chips is to find a layout with

minimal area, further the total wirelength has to be minimized

Due to its complexity, the physical design is normally broken in various sub-steps:

1. First the circuit has to be partitioned to generate some (up to 50) macro

cells.

2. In the floorplanning phase the cells have to be placed on the layout surface.

3. After placement the global routing has to be done. In this step the `loose'

routes for the interconnections between the single modules (macro cells) are

determined.

4. In the detailed routing the exact routes for the interconnection wires in the

channels between the macro cells have to be computed.

5. The last step in the physical design is the compaction of the layout, where it

is compressed in all dimensions so that the total area is reduced.


This classical approach of the physical design is strongly serial with many

interdependencies between the sub-steps.




This course is update every week


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Who this course is for:
  • all the undergraduate ,graduate and working professionals whom are in need to have a quick and appropriate knowledge platform.
  • They would get necessary and required information with crystal clear diagrams and graphics.
Course content
Expand all 17 lectures 04:28:18
+ Physical Design Flow Overview
2 lectures 58:32

1. Utilization Factor And Aspect Ratio

2. Concept of Pre-placed Cells

3. Power Planning

4. Pin Placement And Logical Cell Placement Blockage

Preview 27:32
+ Placement
3 lectures 27:33
L 3.1-Placement(Netlist Binding and Placement)
06:50
L 3.2-Placement optimization 1
11:52
L 3.3-placement optimization 2
08:51
+ clock tree
8 lectures 02:22:30
L 5.2-Introduction to clock tree Synthesis
17:55
L 5.3-latency and power check (cts)
11:52
L 5.4-Glitches quality Check
27:31
L 6-H tree
27:31
L 7.1-clock tree modelling
08:46
L 7.2-clockl building
18:21
L 7.3-CLOCK TREE OBSERVATION
12:34