Basics and Beyond: STA - Static Timing Analysis

Explore CMOS logic and standard cells in a timing context, revealing how transistor physics, interconnect, load, and drive strength shape gate and propagation delays in STA.

Learn the clock period, latency, and duty cycle in static timing analysis, plus master, generated, and virtual clocks, with constraints and practical examples.

Analyze propagation delay, slew, and skew in static timing analysis, and explain how trade-offs between delay, power, and area shape timing, signal integrity, and clock networks.

This lecture defines arrival and required time, showing AT = Tlaunch + Tlogic delay + Twire delay and RT = Tclock period + Tcapture, with slack = RT − AT.

Master setup time and hold time in static timing analysis for launch and capture flip-flops. Assess slack and violations, consider worst corners and clock skew, and apply fixes with buffering.

Explore timing arcs and unateness, and analyze path delay across multiple paths, distinguishing min and max paths in combinational and sequential logic to support setup and hold analysis.

Explore how the critical path defines the longest circuit delay and how metastability, setup and hold times, and mtbf influence synchronizer design in clock domain crossing.

Explore clock domains, PVT operating conditions, and jitter in static timing analysis. Learn clock-domain crossing, synchronization methods, and how uncertainty and worst corners shape timing safeguards.

explore end-to-end path delays and four path types—edge to edge, storage, ready-to-output, and in-to-out—in static timing analysis, and examine combinational and register-to-register paths with interconnect and gate delays.

Learn how to compute setup slack in static timing analysis by analyzing arrival time versus required time, including clock to Q, data delay, buffer delays, and library setup time.

Explore hold slack calculation in timing analysis, defining data stability after the clock edge. Use arrival time minus required time with min delays and library hold time to verify timing.

Explore setup and hold calculations with in2reg, reg2reg, and reg2out paths, including ridge-to-ridge cases, accounting for input/output delays, buffers, and uncertainties, plus practical fixes for timing violations.

Learn time borrowing in latch-based designs to overcome setup timing violations by using the latch's level-sensitive transparent behavior, contrasting with flip-flops in static timing analysis.

Explore multicycle and half-cycle timing paths, modeling setup and hold constraints across flip-flops and latches, and declare false paths to streamline functional and test mode timing.

Explore minimum pulse width checks in static timing analysis, defining clock quality, modeling constraints in lib and sdc, and fixes like balanced clock trees and glitch-free clock gating.

Explore recovery and removal checks in SDA for asynchronous resets. Define recovery time and removal time, illustrate with flip-flop examples, and show library snippets using 2d interpolation for modeling.

Learn how clock gating and integrated clock gating (ICG) checks optimize power in static timing analysis by disabling idle clocks and delivering glitch-free, latch-based clock domains.

Explore static timing analysis inputs, including gate-level netlists, library and SDC constraints, SDF, MC, and tlb files, and how timing reports and timing windows are produced.

Explore non-linear delay model, CHS model and XM models for accurate timing analysis, linking input transition time and output load with 2D lookup interpolation to predict delays and drive currents.

Explore how active, internal, and leakage power are modeled in libraries for static timing analysis, using a nand gate example to illustrate templates and power reports.

Explore interconnect delay models in static timing analysis, including lumped capacitor, lumped RC, distributed RC, PRC, and Elmore delay. Contrast pre layout predictions with post layout reality.

Extract parasitics with spef files to model interconnect delays and crosstalk for static timing analysis; learn about the IEEE 1481-1999 standard, net fan-out, and post-layout sign-off.

Explore signal integrity in static timing analysis, detailing crosstalk glitches between victim and aggressor nets and mitigation techniques like spacing, shielding, buffers, and multi-layer routing.

Explore on chip variation concepts in timing analysis, including ocv, aocv, pocv, socv, lvf, and derates, and learn how flat and advanced models apply delays across chips.

Explore how common path pessimism removal (cppr) eliminates duplicated pessimism in the arrival and required paths, preventing false setup violations and enabling more accurate slack calculations in deep clock trees.

Explore clock skew concepts, including clock push and clock pull, and how useful skew fixes timing violations while preserving setup and hold margins.

Compare graph based analysis and path based analysis in static timing analysis, highlighting pessimism and accuracy: GBA speeds up runtime with worst-case at merges, while PBA provides path specific, accurate delays for sign-off.

Define core clocks, io constraints, and virtual clocks in the SDC. Model input/output delays and use create clock commands to manage multiple clock domains.

Learn to read negative slack and total negative slack in timing reports across Prime Time, Tempus, and Open Timer, with setup and hold analysis and practical examples.

Learn static timing analysis, launch and capture paths, and how slack reveals violations, while noting common pitfalls and trends in signal integrity, power integrity, and machine learning for timing closure.