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AMBA AXI Infrastructure Based on Xilinx FPGA IPs and Verilog

Name: AMBA AXI Infrastructure Based on Xilinx FPGA IPs and Verilog
Rating: 4.2 (192 reviews)

Explanation of AMBA AXI protocol based on Xilinx Infrastructure, verilog and System verilog

Created byHayk Petrosyan

Last updated 7/2020

English

What you'll learn

ARM AXI Protocol
Xilinx AXI Infrastructure
Xilinx Vivado Tool
FPGA and Verilog
Zynq
System Verilog

Course content

4 sections • 22 lectures • 4h 14m total length

AXI-Stream Speck Review13:25
General Review of the speck, simple explanation what is AXI-Stream and why it is needed. Step through most important features and use model of AXI-Stream Protocol
Master AXI Stream Block design using Verilog7:41
We will design our own AXI-Stream Master protocol. We will define the specification of our block and start coding using Verilog.
Simulation of our AXI-Stream Master using Xilinx Vivado6:15
We will write test-bench and simulate our AXI-Stream Master created in previous lectures. For simulation we will use Xilinx Vivado tool. Also some SystemVerilog test-bench techniques will be shown.
Slave AXI Stream Block design using Verilog6:14
Similar to for AXI-Stream Master designing we will design AXI-Stream Slave block.
Simulate our designed AXI-Stream Master and Slave8:11
We will write test-bench and simulate our AXI-Stream Master created in previous lectures. For simulation we will use Xilinx Vivado tool.
Xilinx Traffic Generator IP basics for AXI-Stream5:38
We will review how to generate AXI-Streams using Xilinx provided AXI-Traffic generator IP. Will discuss the IP parameters and usage. More about this IP we will discuss in coming lectures.
Xilinx AXIS DataWidth and Clock Converter IP8:16
During this lecture we will discuss some of frequently used IPs for AXI-Stream, provided by Xilinx. Mainly 2 IPs will be discuss AXIS DataWidth converter and AXIS Clock converter. I will explain each IP parameters, than run simulations to see their functions.

AXI4-Lite Specification Review16:23
In this lecture we review the ARM specification of AXI-Lite protocol, discuss AXI-Lite main features. Understanding AXI-Lite is very important for having general view of AXI functionality. When we master in AXI-Lite protocol switching to AXI would be very smooth and fun process.
The nice presentation will provide all the AXI-Lite features in simple and understandable way.
Designing our own AXI Lite Master11:06
In the lecture we will design our AXI Lite master block.
AXI Verification IP basics16:44
Short introduction to AXI Slave Verification IP
Verification IP Basics
Simulate our own AXI-Lite Master using AXI Verification IP18:21
Here we simulate our designed AXI Lite master, together with the AXILite verification IP
AXI-Stream FIFO Intro14:00
Introduction to AXI-Stream FIFO, explanation to its main functionality.
AXI-Stream FIFO Example Design6:52
Review AXI-Stream FIFO example design
AXI-Lite to AXI-Stream Conversion using AXIS FIFO13:01
In this lecture we will translate from AXI-Lite to ASI Stream using AXI-Stream FIFO and our design AXIL master module.

AXI Protocol Speck Review - Introduction12:30
Introduction to AXI Specification. Basics of AXI protocol usage and structure - channels.
AXI Protocol Speck Review - Burst Operation16:29
This lectures explains one of the most important features of AXI - Burst operation. Different type of burst operations will be discussed. The AXI control signals for Burst operation will be explained. In the lecture simulation waves will be used for easy understanding.
Calculate addresses for Wrap Burst
AXI Protocol Speck Review - Transaction Attributes10:46
In this video basics attributes of transaction explained such as Write Strobe, narrow and unaligned transfer, response signaling and so on. These attributes are one of most time consuming items for AXI protocol understanding.
AXI Protocol Speck Review - Ordering Model15:13
This is last video of AXI specification review series. In this lecture we will review AXI ordering model, which explains how multiple masters and multiple slaves connect with each other in the system. What should be AXI Interconnect behavioral in a system. Also we will discuss some new signals of AXI protocol, which are needed for advances AXI usage.
AXi Speck better understanding Quiz

Project Overview8:10
General description of the AXI project, what is the main function of the design that we will create.
AXI Traffic Generator IP - AXI_Lite Mode15:28
We will review the AXI traffic generator AXI-Lite mode, understand its basics and how it generates AXI transaction.
AXI Traffic Generator IP - AXI Mode13:33
Here explain AXI Traffic Generator for AXI mode, in detail show how it generates AXI transactions.
AXI BRAM Controller IP7:27
Last part of our AXI project, here the AXI BRAM IP will translate the AXI protocol to BRAM understandable format than write and read data from it.

Requirements

Basics of Electrical Enginearing
Basics of Verilog language

Description

Why AXI?

=========

The answer is simple - there is NO any Soc or complex system, which does not contain AXI. If your work somehow is connected with processor, controller or any other big system than there will be multiple AXI buses in the system. AXI bus is a ARM standard bus, which is supported by all hardware companies e.g. Xilinx, Intel, AMD and so on. And by the advance of AI the AXI is going to be more and more popular.

In this course AXI protocol and its sub-parts will be explained.

Also as a free side knowledge you will study Vivado with its IPs, simulation methods and many more.

Target Students

==============

The course is mainly targeted for FPGA designers, who are using AXI based modules in the design. Also the course will be useful for engineers who is starting to use AXI protocol.

The course is extremely helpful for graduate students who is looking for a new job as a FPGA or Soc Developer, in my previous 3 companies AXI questions were the most often to ask the fresh graduates for hire.

Course Content

==============

In the course mainly the basics of AXI protocol family is explained, which allows students easily understand and use AXI based IPs. This is more practical view of AXI usage allowing for jump start to use AXI based modules. The course does not go to FPGA board level,as the target is AXI protocol and Xilinx provided AXI Infrastucture understanding.The course concentrated on simulation level, not FPGA board running is done.

The AXI protocol is complex enough and sometimes it takes much time to get used to it. Usually the AXI protocol is easy to understand when you are familiar with much easy version of it, which are AXI-Stream and AXI-Lite. The course is based on bottom-up-style. At first I explain AXI-stream protocol, than explain AXI-Lite protocol in detail. We do both of these protocol designs using Verilog.

Than having all that baggage of knowledge we move to AXI protocol.

In the course I tried to review the ARM speck for AXI, hoping that this will help students easily jump in speck reading, after finishing the course.

Special Thanks:

=============

I want to express special thanks to Eduard Vardanyan, from ARM, for his great support in making this course. His profound experience and deep knowledge helped me to explain complex AXI parts simply. Without his help I could not do this.

Caution:

=======

Also I apologize for my English, I tried my best to speak clearly and grammatically correct, however sometimes there are some mistakes. I really hope that my non-native English will not bother students to understand the material.

Course Materials:

===============

All course codes can be downloaded from Github.

Note: If you have software background, I would suggest little bit become familiar with Verilog. There are several lectures which require Verilog and hardware basics.

Who this course is for:

University Students
Field Engineers who just started using AXI protocoal
Experienced Engineers who want to get knowledge about Xilinx other AXI related IPs
Anyone who wants to learn FPGA

AMBA AXI Infrastructure Based on Xilinx FPGA IPs and Verilog

What you'll learn

Explore related topics

Course content

AXI Stream Protocol7 lectures • 56min

AXI-Lite Protocol7 lectures • 1hr 36min

AXI Protocol4 lectures • 55min

AXI Project: RAM Write and Read Data4 lectures • 45min

Requirements

Description

Who this course is for: