ARM GNU Assembly Programming From Ground Up™

Explore the computing device hierarchy by examining transistors, logic gates, adders and multipliers, and learn ARM assembly fundamentals while understanding data and instruction buses between processor and memory.

Explore how binary base-2 powers underlie digital logic, compare base-2, base-10, base-8, and base-16 representations, and learn practical conversion methods using 0b and 0x prefixes for hex and addresses.

Explore how processors encode instructions as bits, how ARM mnemonics map to hex opcodes, and how registers and fields like Rd are encoded across different instruction lengths.

Explore the Arm design philosophy and the RISC architecture, noting Arm as a Cambridge design firm licensing architecture, not hardware, with single-cycle instructions, pipelines, and general-purpose registers.

Explore how the ARM design philosophy blends power efficiency, high code density, and RISC principles to optimize mobile and embedded performance, contrasting with CISC and highlighting flexible endianness.

Explore von Neumann versus Harvard architectures, noting memory sharing versus separate data and instruction memories, single versus dual buses, and two simultaneous memory fetches.

Explore the arm cortex-m register set, r0–r12, banked r13 with msp and psp, r14, r15, and xpsr with apsr epsr ipsr, primask faultmask basepri and control via mrs and msr.

Compare the Cortex-M vector table with the ARM 70DMI table, outlining exception types, numbers, memory addresses, and the least significant bit set to one for thumb instruction execution.

Explore the ARM, Thumb, and Thumb-2 instruction sets, comparing 32-bit ARM instructions with 16-bit Thumb. Learn how Thumb-2 blends 16- and 32-bit forms and why some cores run only Thumb-2.

Explore predefined register names in ARM assembly, including r0–r15, a1–a4, sp, lr, pc, cpsr, spsr, and apsr, and learn how a1 maps to r0 for readability.

Learn how directives, or pseudo-ops, guide the assembly process, not execute code, using .thumb, .syntax, .cpu, .section, .global, .equ, .end, .space, .align, .req, .byte, .hword, .word, and .quad.

Explore unary and binary assembly operators in ARM assembly, including modulo, rotate left, shifts, and bitwise operations like and, or, xor, with Keil and GNU formats.

Use the .req directive to rename registers with symbolic names like val1, val2, and sum; move values into r1 and r2 and add to store the result in r3.

Allocate memory space with the .space directive in the .data section, store values 5, 4, and 200 at labels A, D, and C, and verify them in RAM.

Demonstrates swapping two 32-bit registers in ARM GNU assembly using xor instructions, swapping r0 and r1 loaded with 0xbabeface and 0xdeadbeef through a three-step eor sequence.

Learn how load-store instructions move data between memory and registers in ARM, using LDR/STR variants for byte, halfword, and 32-bit data, with base-plus-offset addressing and left shifts.

Explore frequently used load/store instructions in ARM GNU assembly, including ldrh, ldrsh, and ldrsb, showing how halfword and byte data are loaded and sign-extended into registers.

Learn how to store data in memory using ARM GNU assembly with str and ldr instructions, automatic address increments, and addressing modes like [r9, r5, lsl#3] and [r0,#4]!

Learn pre-indexed addressing in arm gnu assembly, using [rn,#offset] with optional ! to update rn; the effective address is rn plus offset, as in str r0,[r1,#12].

Explore post-indexed addressing in assembly, where the effective address uses the unmodified base register, then the offset is added and written back to the base register.

Explain endianness and how ARM supports little and big endian through hardware and software, with little endian as default and big endian usable for certain applications like network traffic.

Define memory areas by creating a coefficient table with dcb 0xFE and 0xF9 starting at 0x4000, and observe little endian ordering when reading with ldrb.

Explore how the ARM MOV instruction encodes an immediate value using an 8-bit immediate and a rotate_imm field to fit a 32-bit instruction for loading constants into a register.

Load constants with ldr and its pseudo form, using pc-relative addresses to initialize registers safely; declare SRAM_BASE equ 0x04000000 and load with ldr r0,#SRAM_BASE.

Learn how to load a 32-bit constant into r3 using movw and movt. Movw loads the lower 16 bits; movt fills the upper 16 bits to form the full value.

Load addresses in arm assembly with adr, adrl, and ldr; adr’s 255-byte limit, adrl’s wider ranges, and ldr with = label or = constant references labels and literals.

Create a simple arm gnu assembly program that loads q=2, r=4, s=5 into registers, adds them to obtain 11, and debug with stm32.

Import a function from c into assembly and access a global variable using the .globl directive, ldr r1,=num, str, and bl to call the function with the result in r0.

Export from assembly to c by creating main.c and function.s, exposing number_func with .globl, and calling it from main to return 121 in r0.

Learn how flags in the psr/cpsr control conditional execution, update via the s suffix on the alu instructions, and review arithmetic and logic operations in arm and cortex m architectures.

Explore the N and V flags in ARM GNU assembly, detecting negative results in two's complement via the N bit and overflow with the V bit during adds.

Understand how the Z flag indicates zero results after an operation and how the C flag signals carry conditions for arithmetic, including checks for zero, carry, and 64-bit addition.

Explore compare and test instructions in ARM GNU assembly, including CMP, CMN, TST, and TEQ, and learn how they update CPSR flags and use MRS/MSR to inspect APSR and PSR.

Explore arm boolean operations, including and, or, xor, and bit clear, and learn how the movn instruction uses ones-complement negation to invert bits in a register, with examples.

Explore the barrel shifter between the register bank and the ALU for left and right shifts and rotations, including unsigned and signed shifts and rotates in ARM moves.

Master logical shifts in arm gnu assembly, including left and right shifts and their relation to multiplying or dividing by 2^n; arithmetic shifts preserve the sign bit.

Explore 32-bit rotations in ARM GNU assembly, including left and right wraps like a circular buffer, and 33-bit rotate with the carry flag, demonstrated in ARM assembler and debug view.

Explore simple shift and rotate examples in ARM GNU assembly, including LSL and ROR, with register-based shifts, note that there is no ROL and left rotate equals right rotate 32-n.

Explore 64-bit addition and subtraction on ARM using two 32-bit registers and the carry flag, with adc, subc, and rsc, and learn the reverse subtract variants rsp and rsc.

Explore arm multiplication instructions, including mul, mla, mls, smull, umull, smlal, and umlal. Observe 32-by-32 multiplies yield 32-bit results or 64-bit products, with nz condition code flags and accumulate behavior.

Discover how to multiply by constants on ARM using a barrel shifter with add/sub, generating powers of two and simple combinations in low-power applications without a multiplier array.

Learn how modern ARM cores implement hardware division with the UDIV instruction, measuring about 14 cycles, and how Cortex-M handles division by zero via fault exceptions or zeroing the destination.

Master cortex-m bit manipulation instructions such as bfi, ubfx, sbfx, bfc, and rbit to modify or extract bit fields using lsb and width for industrial and automotive applications.

The lecture demonstrates using the logical left shift (lsl) to double a value: move 0x11 to r0, lsl to r1 (34), lsl again to r2 (68), with STM32 debugging steps.

Learn to add signed numbers in ARM GNU assembly by loading signed bytes with ldrsb from memory into r2 and looping with subs and bne.

Finds the minimum signed value in an array of nine elements by iterating with signed byte loads, updating the current min, and looping until the counter reaches zero.

Learn to solve a more complex equation using ARM assembly by applying logical and arithmetic shifts, computing (A+8B+7C-27)/4 with mov, mla, and asr operations.

Learn to perform division by subtraction in ARM assembly by repeatedly subtracting r1 from r0, incrementing r2, and looping until r0 is smaller than r1 to yield the quotient.

Explore branches and loops in ARM GNU assembly and how hardware engineers try to predict or avoid branches using conditional execution, with concepts like static and dynamic predictors and caches.

Explore how branch instructions affect ARM pipelines, showing how B, BL, and BX modify the program counter and flush the pipeline. Review conditional branches and link register use in ARM.

Explore how cbz and cbnz replace a compare and branch to avoid flag changes in loops. Note restrictions: only r0–r7, limited branch range, and no usage within an IT block.

Explore loops in ARM assembly, implementing while, for, and do while structures with examples, using BNE and CBZ branches and efficient down-count techniques for Cortex M.

Learn how conditional execution avoids branches in arm gnu assembly to speed up code and reduce size, using teq and z flags with gcd examples.

Learn how the ITTE block enables conditional execution in thumb-2 assembly, using the IT instruction with LT and GE inverses to build then and else instructions.

Compute the factorial for four in arm gnu assembly using the if-then block and gt for conditional execution, looping to multiply and decrement until zero, yielding 24.

Explore stacks from hardware memory to software data types, explaining last-in, first-out behavior, push and pop, and how ARM stack pointer R13 tracks the next entry, with two stack types.

Load and store multiple registers with LDM and STM using a base register, aiding stack operations and exception handling; includes IA, IB, DA, and DB addressing.

Explore the push and pop instructions and their shared syntax, with an optional condition code and a comma-separated register list, and note how both exclude the program counter.

Learn to push and pop 32-bit values on the stack using ARM GNU assembly. Load 0xdeadbeef and 0xbabeface into r3 and r4, push them, and pop into r5 and r6.

Explore how microcontroller gpio pins are organized into ports, configured for general or alternate functions, and controlled by direction and data registers, with ahb and apb buses and clock sources.

Develop a gpio driver in assembly by studying microcontroller memory maps and register configurations, using stm32f411 data sheets, reference manual, and the nucleo user guide to locate and configure pins.

Navigate the memory map to locate GPIOA on the AHB1 bus, enable its clock with RCC, and set pin 5 high to turn on the Nucleo board's user LED.

Enable GPIOA clock with the RCC AHB1ENR, set PA5 as output via MODER, and drive PA5 high or low using the GPIOA ODR.

Turn PA5 into an output by enabling GPIOA clock via RCC_AHB1ENR, configuring GPIOA_MODER for PA5, and driving PA5 high with GPIOA_ODR using LED_ON.

Learn to blink an LED by toggling the GPIOA output data register (ODR) using ARM GNU assembly, preserving PA0 for USB, and implementing a one-second delay loop.

Use the bit set/reset register (BSRR) to set and reset GPIO bits, such as PA5, by writing to the BS set bits or BR reset bits, enabling LED toggling.

Develop a gpio input driver by reading PC13 from the input data register (idr) of gpio c, after enabling gpio c and configuring PC13 as input via the mode register.

Implement an input driver in ARM GNU assembly by initializing GPIO, configuring PA5 as output and PC13 as input, reading IDR, and toggling PA5 via BSRR from the active-low button.

Explore adc independent modes on STM32F4, including single channel single conversion, multichannel single conversion, single channel continuous conversion, multichannel continuous conversion, and injected continuous conversion modes.

Understand how analog to digital converters enable data acquisition by translating sensor voltages from transducers into digital numbers, explain ADC resolution, bit steps, and role of vref in step size.

Plan and configure an ADC driver in assembly for an ARM microcontroller, enabling clocks, setting PA1 as analog, and using a software trigger to read the ADC data register.

enable gpio a clock and set pa1 as analog, configure adc clock via apb2enr, and program adc cr2 and sqr registers to use software trigger and start conversion.

Implement the adc read function by starting conversion with SWSTART and waiting for the EOC flag. Read the result from the adc data register and return it in r0.

Test the adc driver and implement led control in arm assembly by using a 3000 threshold to turn PA5 LED on or off.