Arm Barriers 101: Part #2: How barriers work in hardware

Name: Arm Barriers 101: Part #2: How barriers work in hardware
Rating: 5.0 (5 reviews)

Interconnects, Shareability domains, and what the hardware is doing when we execute a barrier in software.

Created byAsh Wilding

Last updated 5/2025

English

What you'll learn

Discover how Arm AMBA-based cache coherent interconnects work.
Explore how Shareability domains are defined in hardware.
Visualise memory transactions flowing through the interconnect fabric.
Learn how barriers work when being broadcast onto the interconnect for it to handle on behalf of the CPU.
Learn how barriers work when they are being handled internally to the CPU.

Course content

1 section • 9 lectures • 3h 12m total length

Interconnects and snoop requests17:02
Explore how Arm memory barriers enforce ordering through cache coherent interconnects, with home nodes serializing transactions via snoop requests and read shared flows to cache lines.
Sequencing of coherent writes19:56
Defining Shareability domains in hardware16:54
Explain how inner and outer shareable domains define cache coherence across MP core clusters on a CCI-400 interconnect, using broadcast inner and broadcast outer signals and read no snoop.
Shareability on modern AMBA systems20:50
Explore how shareability domains evolve in amba-based systems, from inner and outer domains to DSU snooping and interconnect behavior, and how barriers affect cache coherence.
Broadcasting barriers onto the interconnect23:57
explore how memory barriers are broadcast onto the interconnect, establishing order across inner and outer shareable domains and illustrating the limitations of this hardware technique.
Distributed mesh network propagation24:37
Explore how barriers propagate in a distributed mesh interconnect, enforcing order across multiple home nodes by splitting barriers, and ensuring a single path and no overtaking.
DMA-capable peripheral devices26:38
Explain how barriers enforce memory ordering for dma capable devices in io space, comparing non cacheable and device type accesses with cacheable paths and when to use outer shareable dmb.
Handling barriers internally to the CPU18:05
Quiz24:03

Requirements

Beginner friendly!
Assumes no prior Arm Architecture experience.
Some basic C/C++ programming experience is recommended, but not required.
Strongly recommended to take our "Arm Barriers 101: Part #1: Getting started with barriers" course first.

Description

Welcome to Part 2 of our Barriers 101 training course, a comprehensive deep dive on barriers in the Arm® Architecture.

This course is suitable for software engineers working on Arm-based platforms on system-level software, from down at the firmware layer all the way up through to the kernel, hypervisor, and device drivers.

In these lessons, you'll learn:

How Arm AMBA®-based cache coherent interconnects work.
How Shareability domains are defined in hardware.
How barriers work when they're being broadcast onto the interconnect.
How barriers work when they're being handled internally to the CPU.

From beginner to expert: Our courses are suitable for all levels of experience, whether you're already a seasoned veteran of the Arm Architecture or you're seeing Arm Barriers for the very first time.

How it really works: Our courses go both broader and deeper on the topic of barriers than anyone else; we show you how things really work, and more importantly, why.

Learning is doing: Reinforce your learning with 30 multiple-choice quiz questions including a video walkthrough of each question and answer.

Recognised trainer: Our courses are written and produced by Ash Wilding, formerly one of Arm's lead technical trainers and a kernel engineer at both Amazon AWS and Apple.

Who this course is for:

Engineers at all experience levels working on Arm-based platforms.
Firmware Engineers.
Kernel Engineers.
Hypervisor Engineers.
Device Driver Engineers.