Udemy
    •  
    •  
    •  
    •  
    •  
    •  
    •  
    •  
Subscribe
Turn what you know into an opportunity and reach millions around the world.
Learn More
Your cart is empty.
Keep shopping
Arm Barriers 101: Part #1: Getting started with barriers
Rating: 5.0 out of 5(8 ratings)
28 students

Arm Barriers 101: Part #1: Getting started with barriers

What are barriers, and why do we need them?
Created byAsh Wilding
Last updated 5/2025
English
English

What you'll learn

  • Discover why Arm defines a weakly-ordered memory model
  • Explore the rules dictating whether two memory access may be reordered
  • Learn how to use barriers in software to manually enforce ordering
  • Learn how to descope barriers to mitigate any potential impacts on system performance

Course content

1 section • 10 lectures • 3h 5m total length

  • Why weakly-ordered?16:11

    Explore Arm's weakly ordered memory model and its reordering of memory accesses. Learn how barrier instructions enforce ordering and enable memory optimizations.

  • System-level reordering12:11

    Examine Arm's weakly ordered memory model and how a cache-coherent interconnect with mesh topology and home nodes enables reordering of writes, while barriers establish correct ordering across the system.

  • Dependencies and successors19:13

    Arm's weakly ordered memory model permits reordering of non dependent loads and stores; data and address dependencies, and local read/write successors, determine barrier use for correct message passing.

  • Idempotence and speculation18:13
  • Data Memory Barriers13:13

    Explore data memory barriers in ARM A64, including DMB variants and sy, ld, and st scopes, and how to minimize barrier cost in a two-CPU message-passing scenario.

  • Shareability domains17:22

    Learn how data memory barriers use DMB qualifiers and shareability domains to control memory ordering, with inner and outer shareable scopes, and when to use each for performance.

  • Conventions and expectations15:51
  • Atomics and synchronization26:18
  • Workshop23:55
  • Quiz22:38

Requirements

  • Beginner friendly!
  • Assumes no prior Arm Architecture experience.
  • Some basic C/C++ programming experience is recommended, but not required.

Description

Welcome to Part 1 of our Barriers 101 training course, a comprehensive deep dive on barriers in the Arm® Architecture.

This course is suitable for software engineers working on Arm-based platforms at any level of the software stack, from down at the firmware layer all the way up through the kernel, hypervisor, device drivers, and user-space applications.

In these lessons, you'll learn:

  • Why Arm defines a so-called "weakly-ordered" memory model.

  • The rules dictating whether two memory accesses may be reordered.

  • How to use barriers in software to manually enforce ordering.

  • How to descope barriers to minimise any potential impacts on system performance.

From beginner to expert: Our courses are suitable for all levels of experience, whether you're already a seasoned veteran of the Arm Architecture or you're seeing Arm Barriers for the very first time.

How it really works: Our courses go both broader and deeper on the topic of barriers than anyone else; we show you how things really work, and more importantly, why.

Learning is doing: Reinforce your learning with a workshop session tackling various barrier scenarios from first principles, followed by 30 multiple-choice quiz questions with a video walkthrough of each question and answer.

Recognised trainer: Our courses are written and produced by Ash Wilding, formerly one of Arm's lead technical trainers and a kernel engineer at both Amazon AWS and Apple.

Who this course is for:

  • Engineers at all experience levels working on Arm-based platforms.
  • Firmware Engineers.
  • Kernel Engineers.
  • Hypervisor Engineers.
  • Device Driver Engineers.
  • Application Developers.

Report abuse