ARM Assembly Language From Ground Up™ 1

Explore the computing device hierarchy from transistors to processor architecture, and learn how assembly language programs control memory, buses, and operations like multiplying floating point numbers on ARM.

Explore how binary (base 2) underpins computer arithmetic, convert between bases: binary, decimal, octal, and hexadecimal, and use 0b and 0x notations, with four binary digits per hex digit.

Discover the assembly workflow from source to executable, using the assembler, directives, and linker to produce object files and final executables, with debugging and symbols in ELF and DWARF.

Demonstrates how 1s and 0s become instructions by mapping bit patterns to mnemonics, using hexadecimal notation, and understanding Arm instruction fields like opcode, Rd, and 8-bit immediates.

This lesson introduces assembly syntax by detailing four fields separated by spaces or tabs: label (optional), opcode, operand, and comment, with an example using store_routine STR R0,[R1].

Explore Arm's design philosophy and the risc architecture, emphasizing the reduced instruction set and single-cycle execution. Understand how pipelines, abundant general purpose registers, and compiler-driven design influence hardware and software.

Explore the ARM design philosophy—small, power-efficient cores for mobile and embedded devices with high code density—contrast RISC and CISC, and note ARM's endianness options.

Explore four hardware components of an ARM-based embedded device—the core, memory, controllers, and buses—and how the AHB arbiter and AHB-APB bridge link peripherals like RTC, USART, Ethernet, and timers.

Understand ARM bus technology and the AMBA protocol, including bus master and slave roles, physical and protocol levels, and AHB, ASB, and APB buses that enable higher throughput.

Explore the memory hierarchy in ARM embedded systems, from cache and main memory to ROM, flash ROM, DRAM, SRAM and EPROM, and understand memory width and impact on performance.

Explore memory mapped peripherals on ARM processors, using register offsets from peripheral base addresses, and learn how memory and interrupt controllers configure devices, timing, and standard versus vectored interrupts.

Compare von Neumann's single-bus stored-program architecture with Harvard's dual-bus design featuring separate data and instruction memory. Harvard enables two simultaneous memory fetches, unlike von Neumann's unified memory.

Explore how cache and tightly coupled memory extend the ARM core with fast local memory, enabling unified or separate caches and deterministic real-time performance with TCM.

Explore memory management extensions for ARM cores, including the MPU, MMU, and memory protection concepts. Learn how translation tables provide virtual to physical address mapping with access permissions.

Explore how ARM co-processors extend the core by adding instruction set extensions and configuration registers, including hardware floating point on the cortex M4, with up to 16 co-processors.

From a programmer's perspective, the ARM architecture is explained using binary digits and data types—8-bit bytes, 16-bit half words, and 32-bit words—covering data storage and invalid instruction handling.

Explore ARM architecture and processor modes in Cortex-M and ARM cores, from ARM and Thumb instruction sets to privilege and exception modes like supervisor, abort, and interrupts.

Explore how ARM7TDMI registers form the core storage, detailing the register bank, r15 program counter, cpsr, sp, and lr, plus mode-specific banked registers for interrupts and Thumb/ARM states.

Explore the arm7tdmi vector table and its designated addresses in external memory that handle reset, interrupts, and other events, guiding the processor to the correct handlers via branch instructions.

Explore the cortex-m register model, compare it with arm7tdmi, and learn about 17 general purpose registers, msp and psp banked stacks, r14 and r15, and xpsr with apsr, epsr, ipsr.

Compare the cortex-m vector table to the arm7tdmi vector table, noting each exception number and address, while the lsb must be 1 and cortex-m uses the thumb-2 instruction set.

Explore how data flows through the ARM core—from the data bus and registers to the ALU and barrel shifter—within a von Neumann, RISC, load-store architecture.

Explore how a simple three-stage pipeline fetches, decodes, and executes instructions to speed up execution, illustrating pipeline filling and achieving one instruction per cycle.

Explore the ARM processor family across ARMv7-A, ARMv7-R, and ARMv7-M architectures plus Cortex-A, Cortex-R, Cortex-M lines, with ARM, Thumb, and Thumb-2 instruction sets, and learn cross-family assembly.

Introduce the Cortex-A and Cortex-R families, showing Cortex-A targets smart devices like smartphones with large caches and graphics support, while Cortex-R enables real-time, safety-critical applications in cars and medical devices.

Explore the Cortex-M microcontroller family from M0 to M7, highlighting low-power wearables, DSP-capable M4/M7, and hardware encryption in M23/M33 for IoT security.

Explores programmer's perspective of the arm processor, detailing eight components (alu, barrel shifter, mac, register file, instruction decoder, address register, incrementer, sign extend) and three instruction sets (arm, thumb, thumb-2).

Identify the assembly module structure by examining area and code blocks, the read-only code section, the entry point, and the end directive, then explore export and startup.s usage.

Explore the ARM, thumb, and thumb-2 instruction sets, compare 32-bit ARM instructions with 16-bit thumb and 32-bit thumb-2, and note Cortex-M3/M4 cores run only thumb-2 and how compilers decide size.

Explore predefined ARM register names such as R0–R15, a1–a4, sp, lr, pc, cpsr, spsr, and apsr, and learn how to rename registers for readability and declare custom ones.

Learn frequently used directives that control the assembly process, such as area, thumb, code, data, space, end, and equ, plus dcb, dcd, and their GNU and Keil equivalents.

Create a simple ARM assembly project using a startup file, configure a board or simulator, add an assembly file with directives and a main export, and step through basic instructions.

Build a simple arm cortex m4 assembly project without startup file by defining a stack, a minimal vector table, and a custom reset handler.

Learn how to allocate memory using the space directive in ARM assembly, define data areas, initialize values, and verify memory in SRAM.

Explore unary and binary operators in ARM assembly, including syntax in Keil and GNU formats and common bitwise operations such as shl, shr, and, eor, or, mod, and rol.

Swap the contents of r0 and r1 on a cortex-m4 by using the exclusive OR instruction in a three-stage sequence, loading babeface and deadbeef and validating the results.

Rename registers with the RN directive by aliasing R1 and R2 as VAL1 and VAL2 in a Cortex-M4 project, then move 0x25 and 0x34 and add to SUM.

Explore load-store instructions and addressing as you review the memory system, memory maps, and allocations in Cortex-M microcontrollers like STM32, including 8-bit versus 32-bit memory and ROM and RAM.

Learn how load-store instructions move data between memory and registers using ldr/str and variants like ldrb/strb and ldrh/strh. Understand base plus offset addressing, effective addresses, and pre-indexed and post-indexed modes.

Explore load and store instructions for words, halfwords, and bytes, and see how LDRH and LDRSH/LDRSB use sign extension to interpret memory data.

Learn how ARM load and store instructions move data between registers and memory, use effective addresses, automatic increment, and perform byte and 32-bit stores.

Explore pre-indexed addressing in ARM assembly: compute the address by adding an offset to the base register for load and store, and update the base register with the exclamation mark.

Learn post-indexed addressing in ARM assembly, where the effective address uses the unmodified base register and the offset updates the base register after the transfer.

Understand endianness and how ARM stores 32-bit data in memory, comparing little endian and big endian layouts, with default little endian and the bigend pin as a configuration option.

Define memory areas by creating an 8-bit coefficient table with dcb and using dcd for 32-bit words, reading values with ldrb from 0x400, then interpret memory as little endian.

Learn to copy data between memory locations by filling a ram block with dead beef and transferring it to another ram area via two subroutines, fill and copy.

Explore how constants are encoded in the mov instruction, including the 8-bit immediate and rotate_imm, and how loading constants into a register fits ARM 32-bit and Thumb 16-bit designs.

The arm rotation scheme uses a barrel shifter to rotate an 8-bit value inside a 12-bit instruction, generating many 32-bit constants in registers. For example, 0xff rotated yields 4080.

Learn how to load constants in ARM assembly using the LDR instruction and the equals pseudo-instruction, including loading via the program counter with displacement and safely handling constants like SRAM_BASE.

Use movw and movt to load 32-bit constants: movw handles the lower 16 bits and movt fills the upper 16 bits, often used in pairs for register r3.

Load addresses in arm assembly with adr, adrl, and ldr instructions. Switch from adr to adrl when out of range, and use label references and literals for subroutines and constants.

Compute P = Q + R + S in ARM assembly using move and add instructions; set Q=2, R=4, S=5, and store the result in R0.

Store constants in memory, load them into registers, and compute P = Q + R + S using assembly on a cortex-m4, with a data area and ldr instructions.

Learn register indirect addressing in ARM assembly by using a pointer to a values block, loading Q, R, and S via offsets, computing P = Q+S+R, and storing the result.

refine an arm assembly project by using numeric offsets and three registers to load q, r, and s and compute q plus r plus s in r2.

Explore how arithmetic and logic instructions use status flags to control conditional execution, updating PSR/CPSR registers with the s suffix, and perform fast, space-efficient digital arithmetic.

See how the N flag marks negative results in two's complement by the MSB, and how adds sets the N bit in the PSR, with V flag overflow examples.

Learn how the z flag indicates a zero result and how the carry flag is set when addition reaches 2^32 or a subtraction is positive, enabling 64-bit addition.

Compare and test instructions such as cmp, cmn, tst, and teq update condition codes and reveal register values, while mrs and msr read or modify cpsr/psr for flag checks.

Explore ARM boolean operations with two-register operands, including the moven one's complement negation, and the and, or, xor, and bit clear instructions for zeroing selected bits.

Explore how the ARM subs instruction updates the PSR flags by subtracting values and observing the N, Z, and carry outcomes in a Cortex-M4 debug session.

Experiment with the carry flag in arm assembly by loading values into registers, performing add with carry via adc, and verifying carry behavior on the stm32f4 cortex-m4.

Demonstrate how the overflow and carry bits work in Arm architecture by loading large numbers into registers and performing chained adds that accumulate carries in r9, with debugger feedback.

Explore shifts and rotations in ARM processors via the barrel shifter between the register bank and ALU, enabling 32-bit constants and moves, with unsigned and arithmetic shifts and two rotates.

Learn logical shifts: move bits left or right, fill discarded spaces with zeros, and relate to multiplying or dividing by powers of two; sign preservation occurs with arithmetic right shift.

Explore 32-bit rotation as the ends join like a circular buffer, with MSB becoming the LSB, and see a 33-bit rotate using the carry flag in the assembler debug view.

Explore shift and rotate operations using LSL, LSR, and ROR with registers like R4, R6, and R3, and learn how 32-bit rotation can be achieved without a rol instruction.

Demonstrates the logical shift left (lsl) instruction in ARM assembly, showing how loading 0x11 into r0 and shifting to r1 and r2 multiplies by two in a simulator.

Explore arm assembly arithmetic, including addition, subtraction, and reverse subtraction with the carry flag, using adc, sbc, and rsc, and see 64‑bit operations across 32‑bit registers like r0–r5.

Create an ARM assembly program that finds the dataset maximum value. Initialize count and max, loop with CMP and branches, update max, and return in r1.

Practice adding signed numbers in arm assembly by loading signed data with the load sign byte. Extend to 20 sixteen-bit numbers and adjust the counter and increment.

Identify the minimum signed value in a signed data set by writing an arm assembly program, using sign-extension, a loop, and interpreting results in two's complement on cortex-m4.

Explore saturated math operations in arm assembly, preventing overflow when saturating 32-bit values to 16-bit, and using ssat instructions with the apsr sticky bit to keep data within limits.

Explore ARM multiplication instructions, including mul long variants, umlal, smlal, mla, and mls, and understand 32- and 64-bit results, signedness, accumulation, and condition codes.

Leverage the inline barrel shifter with add and subtract to perform constant multiplications, including powers of two, in a single cycle, demonstrating multiply-by-five and multiply-by-seven techniques.

Explore solving a complex ARM assembly equation using logical and arithmetic shifts. Learn loading constants into registers, performing shifts, multiply-accumulate steps, and final division by four on cortex-m4.

Explore how modern ARM processors implement hardware division with the you div instruction for r1 divided by r2, and the two division-by-zero options in Cortex-M: exception or zero.

Demonstrate division by subtraction in ARM assembly on cortex-m4. Load numerator into r0 and denominator into r1, subtract repeatedly, and count updates in r2 until r0 < r1.

Explore how DSP instructions on Cortex-M4, Cortex-M7, Cortex-M23, and Cortex-M33 processors multiply two 32-bit operands to produce a 64-bit product, add an accumulated value, and handle q31 data formats.

Master fractional notation and arithmetic in assembly, illustrating how 32-bit bit patterns become signed or unsigned values, with decimal and binary points yielding fractions such as 5.5 and 2.75.

Master Cortex-M bit manipulation instructions like BFI, UBFX, SBFX, and BFC that insert, extract, or clear bit fields, using LSB and width to locate and size the fields.

Understand Q notation by representing numbers as scaled binary fractions using powers of two. Align binary points, convert e, pi, and sqrt(2) to Q notation.

Explore branches and loops in ARM assembly and how conditional execution can avoid certain branches, while hardware uses predictors and caches to manage them.

Explore how branch instructions affect the ARM pipeline by examining B, B.L., and B.X with conditional and unconditional branches, and how program counter writes alter flow.

Demonstrates using cbz and cbnz to compare and branch without changing flags, replacing cmp with a single instruction, with constraints: r0–r7, 4–130 byte branch, not in an it block.

Explore loops in assembly, including while, for, and do-while, translated from C. Use ARM and Cortex-M techniques like cbz and b for efficient looping.

Explore conditional execution in ARM assembly by preconditioning instructions to bypass unnecessary work, reducing branches and pipeline stalls, with teq-driven flag checks and GCD examples.

Explore the IT block (if-then) in ARM thumb assembly to build conditional execution without branches, using T and E fields to denote then and else.

Write a factorial routine in assembly using the if-then block, compare, and multiply. Observe how it initializes registers, tests n against zero, and iterates until completion.

Explore how microprocessors search memory data using tables and how to create lookup tables, offering efficient function implementations like log, tan, or sign with trade-offs in memory and precision.

Show how ARM addressing modes support pre indexed addressing with offsets to access a 32-bit lookup table; scale element numbers by 4 and use R5 as base, R4 for offsets.

Construct a floating-point lookup table in ARM assembly by storing constants like pi, e, and 1.0 as hexadecimal data, enabling the FPU, and using offsets to access table entries.

Construct a floating-point lookup table version 2 by labeling constants (c1, c2, c0, c10, pi, e), loading them by label into registers, and multiplying to verify results in the debugger.

Create a sine lookup table from 0 to 90 degrees in C, store the values in a file, then load them into assembly to compute sine rapidly.

Pass the angle as an argument, determine its quadrant, compute the reference angle in the first quadrant, and fetch the sine from a lookup table, negating for the relevant quadrants.

Develop an arm assembly program that uses a sign lookup table to rapidly compute sine for an input value, employing quadrant checks and adr addressing.

Explore jump tables in arm assembly to replace branches with address-based subroutines, using a program counter driven table to perform add and subtract operations.