
Download the Standard Logic 1164 Library Package in the Resources section
Download the Standard Logic Arithmetic Library Package in the Resources section
Download the Numeric Bit Library Package in the Resources section
Download the Standard Logic Text IO Library Package in the Resources section
Create a test bench to test the functionality of a 3-to-8 Decoder in VHDL, by setting up a testbench.
Create a test bench to test the functionality of a Full Adder in VHDL, by setting up a testbench.
Before doing this lecture, please go ahead and download the Vivado Simulator from the following link:
https://www.xilinx.com/support/download.html
Select the latest version (2019.2) as of the time of this lecture. And select the Windows Self Extracting Installer Link (see picture below in Resources). You will need to register (create an account) with Xilinx prior to downloading the software. So go ahead and do that first, log in to Xilinx, and then click on the link above.
Once the extractor downloads, the installation will begin. Make sure to select Vivado Web pack (the free version of the tool), which will allow you to run simulations without any license. After the installation is complete, you can then double click on the Vivado tool on your desktop and the Vivado Suite Tool should open on your computer.
After you have successfully installed Vivado, and opened the tool, go ahead and download the VHDL.zip file from the Download Resources in this section. These will be the files you will use for this section to run the testbench simulation using Vivado.
See Lecture 29 for download information for the Vivado tool (if you haven't downloaded it already).
An Introduction To VHDL is an introductory course that teaches the basics of VHDL, so students have a beginner understanding of writing VHDL code. It presents a set of simple and commonly used features of the VHDL language, so that students can begin writing models of digital logic circuits in VHDL. Numerous examples are included within the course, that explain the different formulations of the language constructs and their semantics.
Course Outline:
Introduction to VHDL: Understanding the purpose and applications of VHDL in digital design.
Getting Started with VHDL: Setting up your development environment and writing your first VHDL code.
VHDL Syntax and Data Types: Mastering VHDL syntax, data types, and basic constructs.
Behavioral Modeling: Writing VHDL code to describe the behavior of digital circuits.
Structural Modeling: Designing digital circuits using component instantiation and structural modeling techniques.
Sequential Logic Design: Understanding flip-flops, registers, counters, and state machines in VHDL.
Concurrent Logic Design: Exploring concurrent signal assignments, processes, and sensitivity lists.
Advanced Topics: Delving into advanced VHDL features such as generics, packages, and testbenches.
FPGA Programming with VHDL: Applying VHDL to program FPGA devices for custom digital designs.
An Introduction To VHDL provides a great beginner level introduction to the VHDL language, that can be understood both by digital logic design enthusiasts, as well as electrical engineers and those interested in learning VHDL language to broaden their knowledge of the digital world.
By the end of this course, you'll have the basic knowledge and skills to confidently write, simulate, and synthesize VHDL code for various digital design applications. Whether you're pursuing a career in digital design or simply passionate about electronics, this course will empower you to take your first steps into the exciting world of VHDL programming. Join us today and embark on your journey to mastering VHDL!