Advanced VHDL for Verification

Name: Advanced VHDL for Verification
Rating: 4.6 (151 reviews)

Generics, Alias, Records, Mutli-dimensional arrays, TestIO, Signal Hierarchy, and Bus Functional Models

Last updated 7/2020

English

What you'll learn

Advanced VHDL for verification, including TextIO, configurations, generics, records, BFM, multi-dimensional arrays, and access types.

3 sections • 10 lectures • 4h 25m total length

VHDL Configurations22:03
Understanding VHDL Configurations and how to use configurations in simulation.
VHDL Arrays24:09
VHDL Generics, Records and Multi-dimensional arrays for RTL and behavioral design and verification.
VHDL Memories35:06
Using multi-dimensional arrays to model large memories, and how to infer RTL memories with arrays.
Asynchronous FIFO12:21
Discussion on designing asynchronous FIFOs with inferred RTL arrays.
RAM and FIFO Lab

Experience in VHDL RTL design. Introduction to VHDL course completion recommended.

The advanced VHDL course includes advanced RTL features as well as verification behavioral capabilities :

- VHDL Configurations

- VHDL Arrays

- Modeling memories in VHDL, creating inferred memories in RTL

- Modeling and inferring FIFOs in VHDL

- VHDL Signal Hierarchy

- VHDL Generics , Records, and Alias

- VHDL File I/O , and TextIO

- Creating pseudo-code for simulations

- Developing VHDL Bus Functional Models

VHDL RTL or Verification engineers who want to use the VHDL language to improve verification.