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System Verilog : Fully Hands on Learning Experience
Rating: 4.5 out of 5(1 rating)
329 students

System Verilog : Fully Hands on Learning Experience

Master SystemVerilog with hands-on RTL coding, verification, assertions, UVM basics & industry-level projects
Created byAK APT LOGICS
Last updated 4/2026
English

What you'll learn

  • System Verilog Comments
  • System Verilog Value System
  • System Verilog Enhancec Literal
  • System Verilog Floating/Exponential Numbers

Course content

1 section • 5 lectures • 1h 10m total length

  • System Verilog Comments5:00
  • System Verilog Value System4:22
  • System Verilog Enhanced Literal36:44
  • System Verilog Floating Point Numbers/Exponential Numbers17:42
  • System Verilog 4 State Datatype6:40

Requirements

  • Digital Electronics and Verilog HDL

Description

This course is a complete hands-on guide to mastering SystemVerilog for VLSI design and verification, specifically designed for students, freshers, and aspiring RTL/Design Verification engineers. Whether you are starting from the basics or looking to strengthen your practical skills, this course will help you build a strong foundation with real industry-oriented concepts.

In this course, you will learn SystemVerilog fundamentals and syntax, followed by RTL design techniques using SystemVerilog. You will gain hands-on experience in writing efficient and scalable testbenches, understanding assertions, and applying verification methodologies. The course also introduces you to UVM (Universal Verification Methodology) basics, helping you understand how modern verification environments are built in the semiconductor industry.

You will work on real-time examples and projects such as ALU, FIFO, UART, and FSM design and verification, along with simulation and debugging using waveforms. Industry tools like ModelSim, QuestaSim, Vivado, VS Code, and EDA Playground will be used throughout the course, along with GTKWave for waveform analysis.

This course follows a fully hands-on learning approach, ensuring you gain practical exposure to real VLSI design and verification flow. It is suitable for ECE/EEE students, VLSI aspirants, and engineers preparing for RTL design and verification roles.

By the end of this course, you will be confident in designing and verifying digital systems using SystemVerilog and ready to step into the VLSI industry with job-ready skills.

Who this course is for:

  • Beginner Who has good amount of knowledge in Design and to Step into the Verification

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